參數(shù)資料
型號: PCD5096H
廠商: NXP SEMICONDUCTORS
元件分類: 編解碼器
英文描述: Universal codec
中文描述: A/MU-LAW, PCM CODEC, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 19/52頁
文件大?。?/td> 222K
代理商: PCD5096H
1997 Jan 22
19
Philips Semiconductors
Preliminary specification
Universal codec
PCD5096
8.3.7
C
ONTROL
R
EGISTER
5 (CR5)
CR5 controls the general purpose I/O pin IO0.
Table 23
Control Register 5 (address 7DH)
Table 24
Description of CR5 bits
Note
1.
Depending on the DSP program, the contents of CR5 might be overwritten by the DSP as soon as the reset is
inactive.
8.3.8
C
ONTROL
R
EGISTER
6 (CR6)
CR6 controls the general purpose I/O pin IO1.
Table 25
Control Register 6 (address 7EH)
Table 26
Description of CR6 bits
Note
1.
Depending on the DSP program, the contents CR6 might be overwritten by the DSP as soon as the reset is inactive.
1
0
IODIR0
IO0
BIT
SYMBOL
DESCRIPTION
1
IODIR0
Direction control for IO0. If IODIR0 = 1, then IO0 is an input. If IODIR0 = 0, then IO0 is
an output. Input during and after reset; see note 1.
State of IO0
0
IO0
1
0
IODIR1
IO1
BIT
SYMBOL
DESCRIPTION
1
IODIR1
Direction control for IO1. If IODIR1 = 1, then IO1 is an input. If IODIR1 = 0, then IO1 is
an output. Input during and after reset; see note 1.
State of IO1
0
IO1
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