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參數(shù)資料
| 型號： | PCD5096H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編解碼器 |
| 英文描述： | Universal codec |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 222K |
| 代理商： | PCD5096H |
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1997 Jan 22
26
Philips Semiconductors
Preliminary specification
Universal codec
PCD5096
10 I
2
C-BUS INTERFACE
The PCD5096 is programmed by writing to the control
registers (CR0 to CR6) and loading the SDR using the
I
2
C-bus interface. The master on the I
2
C-bus is either a
PCD509x DECT processor or an external microcontroller.
The memory map of the PCD5096 is given in Chapter 8.
It consists of 128 words (16 bits wide) of system data
IOM buffers, IOM control data and DSP parameters) and
7 words (16 bits wide) of control registers mapped at
addresses 78H to 7EH.
The I
2
C-bus interface uses word and byte access to the
RAM and to the control registers. For byte access the
address is not incremented automatically. For word
access the address is incremented after two data bytes
(low, high byte) in order to be able to fill the memory
without a full I
2
C-bus protocol (start, slave address, stop
bits).
The protocol is shown in Figs 12 to 15. I2C_BYTE = 1, for
byte access and I2C_BYTE = 0, for word access.
I2C_BSEL = 1 for selecting the high byte and
I2C_BSEL = 0 for selecting the low byte. For control
registers with less than 8 bits, there is no difference
between word access, high byte access and low byte
access.
The PCD5096 has two pins (A1 and A0) for programming
the slave address. This means that a maximum of four
devices can be located on a board without glue logic.
The I
2
C-bus slave address allocated for the PCD5096 is
shown in Fig.11.
Fig.11 PCD5096 I
2
C-bus slave address.
handbook, halfpage
MBH870
A6
0
R/W
A5
0
A4
1
A3
1
A2
0
A1
A1
A0
A0
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