參數(shù)資料
型號: PCD5096
廠商: NXP Semiconductors N.V.
元件分類: Codec
英文描述: Universal codec
中文描述: 通用編解碼器
文件頁數(shù): 31/52頁
文件大小: 222K
代理商: PCD5096
1997 Jan 22
31
Philips Semiconductors
Preliminary specification
Universal codec
PCD5096
Table 33
Pin redefinition in Codec test loop mode
11.2
Codec test loop signal timing
The TEST_OUTPUT_x signal changes at the falling edge of CLK3, and the signal presented on TEST_INPUT_x is
sampled just before the falling edge of CLK3. Note that the 4f
s
serial PCM data shifted in via TEST_INPUT_x is only used
during the next FS4 HIGH period.
NORMAL MODE
CODEC TEST LOOP MODE
PIN NAME
SIGNAL NAME
I/O
DESCRIPTION
DI
DO
A1
IO1
DCL
IO0
TEST_INPUT_1
TEST_OUTPUT_1
TEST_INPUT_2
TEST_OUTPUT_2
CLK3
FS4
I
108f
s
bitstream or 4f
s
serial data input to Codec 1
108f
s
bitstream or 4f
s
serial data output from Codec 1
108f
s
bitstream or 4f
s
serial data input to Codec 2
108f
s
bitstream or 4f
s
serial data output from Codec 2
3456 kHz bit clock signal (4
×
108f
s
) with 50% duty cycle
32 kHz word synchronization signal (4f
s
), duty cycle = 12/108
O
I
O
O
O
Fig.17 Codec test loop signal timing for 108f
s
1-bit bitstream signals.
handbook, full pagewidth
MBH877
sample moment for 1 bit digital loop mode
sample moment for 1 bit analog loop mode
CLK3
FS4
FS1
TEST_OUTPUT_x
TEST_INPUT_x
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