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參數(shù)資料
| 型號： | PCD5096 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | Universal codec |
| 中文描述： | 通用編解碼器 |
| 文件頁數(shù)： | 20/52頁 |
| 文件大?。?/td> | 222K |
| 代理商： | PCD5096 |
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1997 Jan 22
20
Philips Semiconductors
Preliminary specification
Universal codec
PCD5096
9
IOM
9.1
Features
The IOM block in the PCD5096 is a 4-wire serial interface
performing the following functions:
Digital interface with up to fourteen 64 kbits/s channels
at a bit rate of n
×
256 kbits/s (n = 1, 2, 3, 4 or 8),
complying with the IOM-2 specifications (IOM-2 is a
registered trademark of Siemens AG)
Digital interface with 32 slots/frame and non-doubled
data clock, compatible with the digital interface of some
DTAM speech compression ICs
Autonomous storing/fetching of data to/from the system
data memory (SDR) using internal addressing logic
Byte or word (16 bits) transfer
14 data buffers (byte or word)
Muting of speech data
Local call.
9.2
Pin description
The following pins are used by the IOM-2 interface:
DI
: serial data input with a bit rate of n
×
256 kbits/s
(n = 1, 2, 3, 4 or 8)
DO
: serial data output with a bit rate of n
×
256 kbits/s
(n = 1, 2, 3, 4 or 8). DO is an open-drain pin, as many
devices must be able to write on the same data line in a
time-multiplexed mode. Therefore, DO must be
externally pulled-up.
FSC
: 8 kHz frame synchronization input
DCL
: data clock input. Twice the data transmission
frequency on DI and DO, except in the non-doubled data
clock mode (see Section 9.3).
9.3
Functional description
The digital interface of the PCD5096 can work at several
bit rates; these are specified Table 27. The bit rate is
selected by writing the appropriate 3 bit code, given in
Table 27, into Control Register 1 (address 79H).
The PCD5096 is always a slave on the IOM interface,
which means that both FSC and DCL are inputs. This is
valid for both the IOM modes and the Speech mode.
FSC is an 8 kHz framing signal for synchronizing data
transmission on DI and DO. The rising edge of FSC gives
the time reference for the first bit transmitted in the first slot
of a speech frame. The number of slots per speech frame
depends on the selected data rate. Each slot contains
8 data bits.
DCL is a data clock. Its frequency is twice the selected
data rate in IOM mode. In Speech mode, the DCL
frequency is equal to the data rate (2048 kHz for
2048 kbits/s).
DI is the serial data input. Data coming on DI in packets of
8 bits (A-law PCM encoded data) or 16 bits (linear PCM
data) is stored temporarily in an IOM data buffer, from
where it is processed by the on-chip DSP. On the other
hand, data written into the IOM data buffers by the DSP is
shifted out on pin DO.
There are 14 IOM data buffers, allowing the use of
14 different channels. One channel is 64 kbits/s for A-law
PCM encoded data and 128 kbits/s if linear PCM data is
transferred, in which case two consecutive slots are used.
The Speech mode was implemented to support the codec
interface of some speech compression ICs. This mode is
very similar to the IOM 32 slots mode, the main difference
being the non-doubled data clock. See Section 9.4 for
timing information.
Table 27
IOM modes
IOM2
IOM1
IOM0
MODE
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
These codes deactivate the IOM-2 interface and stop all the transactions on the
IOM bus. This is the default state after reset.
IOM slave mode, 256 kbits/s in 4 slots/speech-frame
IOM slave mode, 512 kbits/s in 8 slots/speech-frame
IOM slave mode, 768 kbits/s in 12 slots/speech-frame
IOM slave mode, 1024 kbits/s in 16 slots/speech-frame
Speech mode, 2048 kbits/s in 32 slots/speech-frame. The Speech mode is
similar to the IOM slave 32 slots mode, but with a non-doubled data clock DCL.
IOM slave mode, 2048 kbits/s in 32 slots/speech-frame
1
1
1
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