參數(shù)資料
型號： PCD5003H
廠商： NXP SEMICONDUCTORS
元件分類： 尋呼電路
英文描述： Advanced POCSAG Paging Decoder
中文描述： TELECOM, PAGING DECODER, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁數(shù)： 36/44頁
文件大?。?/td> 187K
代理商： PCD5003H
1997 Jun 24
36
Philips Semiconductors
Product specification
Advanced POCSAG Paging Decoder
PCD5003
Notes
1.
32768 Hz reference signal: 32 pulses per 75 clock cycles, alternately separated by 1 or 2 pulse periods
(pulse duration: t
RFP
). The timing is shown in Fig.14.
50 Hz reference signal: square-wave.
The fall time may be faster than prescribed in the I
2
C-bus specification for very low load capacitance values.
To increase the fall time external capacitance is required.
Duration depends on programmed bit rate; after reset t
ZSU
= 1.5 bits.
Nominal values; pause in 12th data bit (see Table 12).
2.
3.
4.
5.
POCSAG data timing (1200 bits/s)
f
DI
t
BIT
t
CW
t
PA
t
BAT
data input rate
bit duration
codeword duration
preamble duration
batch duration
SPF byte 01H; bits D5, D4 = 1 0
1200
833.3
26.7
453.3
bits/s
μ
s
ms
ms
ms
480
POCSAG data timing (2400 bits/s)
f
DI
t
BIT
t
CW
t
PA
t
BAT
data input rate
bit duration
codeword duration
preamble duration
batch duration
SPF byte 01H; bits D5, D4 = 1 1
2400
416.6
13.3
226.6
bits/s
μ
s
ms
ms
ms
240
Synthesizer control
t
ZSU
f
ZSC
t
ZCL
t
ZSD
t
ZDS
t
ZDL1
t
ZLE
t
ZDL2
synthesizer set-up duration
output clock frequency
clock pulse duration
data bit duration
data bit set-up time
data load enable delay
load enable pulse duration
inter block delay
oscillator running; note 4
note 5
1
38400
13.02
26.04
13.02
91.15
13.02
117.19
2
bits
Hz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
note 5
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCD5003HB-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder
PCD5003U/10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder
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PCD5008H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX Pager Decoder
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