參數(shù)資料
型號(hào)： PCD5003H
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 尋呼電路
英文描述： Advanced POCSAG Paging Decoder
中文描述： TELECOM, PAGING DECODER, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁(yè)數(shù)： 24/44頁(yè)
文件大小： 187K
代理商： PCD5003H
1997 Jun 24
24
Philips Semiconductors
Product specification
Advanced POCSAG Paging Decoder
PCD5003
7.48
EEPROM access limitations
Since the EEPROM address pointer is used during data
decoding, the EEPROM may not be accessed while the
receiver is active (RXE = 1). It is advised to switch to OFF
state before accessing the EEPROM.
The EEPROM cannot be written unless the EEPROM
programming enable bit (bit D1) in the control register is
set.
For writing a minimum supply voltage V
PG
is required
(2.0 V typ.). The supply current needed during writing (I
PG
)
will be
≈
500
μ
A.
Any modified SPF settings (bytes 0 to 3) only take effect
after a decoder reset. Modified identifiers are active
immediately.
7.49
EEPROM read operation
EEPROM read operations must start at a valid address in
the non-contiguous memory map. Single-byte or block
reads are permitted.
7.50
EEPROM write operation
EEPROM write operations must always take place in
blocks of 6 bytes, starting at the beginning of a row.
Programming a single byte will reset the other bytes in the
same row. Modifying a single byte in a row requires
re-writing the unchanged bytes with their old contents.
After writing each block a pause of maximum 7.5 ms is
required to complete the programming operation
internally. During this time the external microcontroller
may generate an I
2
C-bus stop condition. If another I
2
C-bus
transfer is started the decoder will pull SCL LOW during
this pause.
After writing the EEPROM programming enable bit (D1) in
the control register must be reset.
7.51
Invalid write address
When an invalid write address is used, the column counter
bits (D2 to D0) are forced to zero before being loaded into
the address pointer. The row counter bits are used
normally.
7.52
Incomplete programming sequence
A programming sequence may be aborted by an I
2
C-bus
stop condition. Next, the EEPROM programming enable
bit (D1) in the control register must be reset.
Any bytes received of the last 6-byte block will be ignored
and the contents of this (incomplete) EEPROM block will
remain unchanged.
7.53
Unused EEPROM locations
A total of 20 EEPROM bytes is available for general
purpose storage (see Table 19).
Fig.10 EEPROM organization and access.
handbook, full pagewidth
COLUMN
2
ROW
0
1
2
3
4
5
6
7
0
D7
D0
D7
D0
ADDRESS
POINTER
ROW COLUMN
I/O REGISTER
0
1
0
1
0
0
SPF bits
Synthesizer data
Identifiers
unused bytes
1
I
D
MLC254
1
3
4
5
2
I
D
3
I
D
4
I
D
5
I
D
6
I
D
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