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參數(shù)資料
| 型號(hào)： | PCD5003H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | Advanced POCSAG Paging Decoder |
| 中文描述： | TELECOM, PAGING DECODER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 19/44頁 |
| 文件大小： | 187K |
| 代理商： | PCD5003H |
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1997 Jun 24
19
Philips Semiconductors
Product specification
Advanced POCSAG Paging Decoder
PCD5003
7.28
Real time clock
The PCD5003 provides a periodic reference pulse at
output REF. The frequency of this signal can be selected
by SPF programming:
32768 Hz
50 Hz (square-wave)
2 Hz
1
60
Hz.
The 32768 Hz signal does not have a fixed period: it
consists of 32 pulses distributed over 75 main oscillator
cycles at 76.8 kHz. The timing is shown in Fig.14.
When programmed for
1
60
Hz (1 pulse per minute) the
pulse at output REF is held off while the receiver is
enabled.
Except for the 50 Hz frequency the pulse width t
RFP
is
equal to one decoder clock period.
The real time clock counter runs continuously irrespective
of the operating condition of the PCD5003. It contains a
seconds register
(maximum 59) and a
1
100
second
register
(maximum 99), which can be read or written via
the I
2
C-bus. The bit allocation of both registers is shown in
Tables 16 and 17.
Table 16
Real time clock; seconds register (01H;
read/write)
BIT
(MSB D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
X
1 s
2 s
4 s
8 s
16 s
32 s
not used: ignored when written,
undetermined when read
not used: ignored when written,
undetermined when read
D7
X
Table 17
Real time clock;
1
100
second register (02H;
read/write)
7.29
Periodic interrupt
A periodic interrupt can be realised with the Periodic
Interrupt Counter. This 8-bit counter is incremented every
1
100
second and produces an interrupt when it reaches the
value stored in the Periodic Interrupt Modulus register.
The Counter register is then reset and counting continues.
Operation is started by writing a non-zero value to the
Modulus register. Writing a zero will stop interrupt
generation immediately and will halt the Periodic Interrupt
Counter after 2.55 seconds.
The Modulus register is write-only, the Counter register
can only be read. Both registers have the same index
address (05H).
7.30
Received call delay
Call reception causes both the Periodic Interrupt Modulus
and the Counter register to be reset.
Since the Periodic Interrupt Counter runs for another
2.55 seconds after a reset, the received call delay
(in
1
100
second units) can be determined by reading the
Counter register.
BIT
(MSB D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
X
0 01 s
0.02 s
0.04 s
0.08 s
0.16 s
0.32 s
0.64 s
not used: ignored when written,
undetermined when read
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PCD5003HB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5003U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5008 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX Pager Decoder |
| PCD5008H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX Pager Decoder |
| PCD5008HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
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