參數(shù)資料
型號(hào)： PCD5003
廠商： NXP Semiconductors N.V.
英文描述： Advanced POCSAG Paging Decoder
中文描述： 高級(jí)尋呼POCSAG碼解碼器
文件頁(yè)數(shù)： 25/44頁(yè)
文件大小： 187K
代理商： PCD5003
1997 Jun 24
25
Philips Semiconductors
Product specification
Advanced POCSAG Paging Decoder
PCD5003
Table 19
Unused EEPROM addresses
Note
1.
When using bytes 04H and 05H, care must be taken to
preserve the SPF information stored in
bytes 00H to 03H.
ROW
HEX
0
5
6
7
04 and 05
(1)
28 to 2D
30 to 35
38 to 3D
7.54
Special programmed function allocation
The SPF bit allocation in the EEPROM is shown in
Tables 20 to 24. The SPF bits are located in row 0 of the
EEPROM and occupy 4 bytes.
Bytes 04H and 05H are not used and are available for
general purpose storage.
The contents of SPF (bytes 0 to 3) are read into the
associated logic only when the decoder is reset
(HIGH level in input RST).
Table 20
Special Programmed Functions (EEPROM address 00H)
Table 21
Special Programmed Functions (EEPROM address 01H)
Note
1.
Since the exact establishment time is related to the programmed bit rate, Table 22 shows the values for the various
bit rates.
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
D2
D3
D4
D5
D6
D7
X
X
X
X
X
X
X
1
reserved for future use; logic 0 when read
reserved for future use
reserved for future use
reserved for future use
reserved for future use
reserved for future use
reserved for future use; logic 0 when read
received data inversion enabled
BIT (MSB: D7)
VALUE
DESCRIPTION
D1 and D0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
5 ms receiver establishment time (nominal); note 1
10 ms
15 ms
30 ms
20 ms oscillator establishment time (nominal); note 1
30 ms
40 ms
50 ms
512 bits/s received bit rate
1024 bits/s (not used in POCSAG)
1200 bits/s
2400 bits/s
synthesizer interface enabled (data is output via ZSD, ZSC
and ZLE at decoder switch-on)
voltage converter enabled
D3 and D2
D5 and D4
D6
D7
1
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