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參數(shù)資料
| 型號： | PCD5003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Advanced POCSAG Paging Decoder |
| 中文描述： | 高級尋呼POCSAG碼解碼器 |
| 文件頁數(shù)： | 18/44頁 |
| 文件大小： | 187K |
| 代理商： | PCD5003 |
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1997 Jun 24
18
Philips Semiconductors
Product specification
Advanced POCSAG Paging Decoder
PCD5003
Table 14
Status register (00H; read)
Note
1.
After a status read operation bits D3, D4 and D7 are always reset, bits D1 and D0 only when no second call is
pending. D2 is reset when the RAM is empty (read and write pointers equal).
Table 15
Control register (00H; write)
BIT
(1)
VALUE
DESCRIPTION
D1 and D0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
1
1
1
no new call data
new call received
reserved for future use
reserved for future use
no data to be read (default after reset)
RAM read/write pointers different: data to be read
RAM read/write pointers equal: no more data to read
RAM buffer full or overflow
alert time-out expired
out-of-range
BAT input HIGH or RXE output active (selected by control bit D2)
periodic timer interrupt
D3 and D2
D4
D5
D6
D7
BIT (MSB: D7)
VALUE
DESCRIPTION
D0
D1
1
1
0
1
1
0
1
X
forced call termination (automatically reset after termination)
EEPROM programming enable
BAT input selected for monitoring (status bit D6)
RXE output selected for monitoring (status bit D6)
receiver continuously enabled (RXE = 1, ROE = 1)
decoder in OFF status (while DON = 0)
decoder in ON status
not used: ignored when written
D2
D3
D4
D5 to D7
7.26
Pending interrupts
A secondary status register is used for storing status bits
of pending interrupts. This occurs:
When a new call is received while the previous one was
not yet acknowledged by reading the status register
When an interrupt occurs during a status read operation.
After completion of the status read the primary register is
loaded with the contents of the secondary register, which
is then reset. Next, an immediate interrupt is generated,
output INT becoming active 1 decoder clock cycle after it
was reset following the status read.
Remark
: In the event of multiple pending calls, only the
status bits of the last call are retained.
7.27
Out-of-range Indication
The out-of-range condition occurs when entering fade
recovery or ‘carrier off’ mode. This condition is reflected in
bit D5 of the status register. The out-of-range condition is
reset when either preamble or a valid sync word is
detected.
The out-of-range bit (D5) in the status register is updated
each time the receiver is disabled (RXE
↓
0). Every
change of state in bit D5 generates an interrupt.
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