參數(shù)資料
型號(hào): PCA9560
廠商: NXP Semiconductors N.V.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù): 8/17頁(yè)
文件大?。?/td> 111K
代理商: PCA9560
Philips Semiconductors
Product data
PCA9560
Dual 5-bit multiplexed 1-bit latched
I
2
C EEPROM DIP switch
2003 Jun 27
8
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH-level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
SW00368
DATA OUTPUT
BY RECEIVER
1
2
8
9
S
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
Figure 8. Acknowledgement on the I
2
C-bus
相關(guān)PDF資料
PDF描述
PCA9560D The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
PCB2032V EEPROM
PCB2320DP ISDN Line Interface
PCB2325DP ISDN Line Interface
PCB2391A ISDN, Other/Special/Miscellaneous
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