參數(shù)資料
型號(hào): PCA9560
廠商: NXP Semiconductors N.V.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù): 12/17頁(yè)
文件大小: 111K
代理商: PCA9560
Philips Semiconductors
Product data
PCA9560
Dual 5-bit multiplexed 1-bit latched
I
2
C EEPROM DIP switch
2003 Jun 27
12
SAC CHARACTERISTICS
LIMITS
TYP.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
MUX_IN
MUX_OUT
t
PLH
t
PHL
Select
MUX_OUT
t
PLH
t
PHL
t
R
t
F
C
L
Select
NON-MUXED_OUT
t
PLH
t
PHL
LOW-to-HIGH transition time
28
40
ns
HIGH-to-LOW transition time
8
15
ns
LOW-to-HIGH transition time
30
43
ns
HIGH-to-LOW transition time
10
15
ns
Output rise time
1.0
3
ns/V
Output fall time
1.0
3
ns/V
Test load capacitance on outputs
50
pF
LOW-to-HIGH transition time
30
40
ns
HIGH-to-LOW transition time
9
15
ns
AC SPECIFICATIONS
SYMBOL
PARAMETER
STANDARD MODE
I
2
C-BUS
MIN
0
FAST MODE
I
2
C-BUS
MIN
0
UNITS
MAX
100
MAX
400
f
SCL
t
BUF
t
HD;STA
t
SU;STA
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
t
SU;DAT
t
LOW
t
HIGH
t
F
t
R
t
SP
Operating frequency
kHz
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
Bus free time between STOP and START conditions
4.7
1.3
Hold time after (repeated) START condition
4.0
0.6
Repeated START condition setup time
4.7
0.6
Set-up time for STOP condition
4.0
0.6
Data in hold time
Valid time for ACK condition
2
Data out valid time
3
0
0
0.3
3.45
0.1
0.9
300
50
Data set-up time
250
100
ns
μ
s
μ
s
ns
Clock LOW period
4.7
1.3
Clock HIGH period
4.0
0.6
Clock/Data fall time
300
20 + 0.1 C
b1
20 + 0.1 C
b1
300
Clock/Data rise time
1000
300
ns
Pulse width of spikes that must be suppressed by the
input filters
50
50
ns
NOTES:
1. C
b
= total capacitance of one bus line in pF.
2. t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
3. t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
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