參數(shù)資料
型號(hào): PCA9500
廠商: NXP Semiconductors N.V.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個(gè)2 KB的EEPROM的國內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁數(shù): 15/23頁
文件大?。?/td> 169K
代理商: PCA9500
Philips Semiconductors
Product data sheet
PCA9500
8-bit I
2
C and SMBus I/O port with 2-kbit EEPROM
2004 Sep 30
15
POWER-UP TIMING
SYMBOL
t
PUR1
t
PUW1
NOTE:
1. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters are
guaranteed by design.
PARAMETER
MAX.
UNIT
Power-up to Read Operation
1
ms
Power-up to Write Operation
5
ms
WRITE CYCLE LIMITS
SYMBOL
t
WR1
NOTE:
1. t
WR
is the maximum time that the device requires to perform the internal write operation.
PARAMETER
MIN.
TYP.
(5)
MAX.
UNIT
Write Cycle Time
5
10
ms
Write Cycle Timing
SCL
SDA
8th Bit
Word n
ACK
Stop
Condition
Start
Condition
MEMORY
ADDRESS
t
WR
SW00560
Figure 21.
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