參數(shù)資料
型號(hào): PCA9500
廠商: NXP Semiconductors N.V.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個(gè)2 KB的EEPROM的國(guó)內(nèi)256個(gè)8位每字舉辦的串行CMOS
文件頁(yè)數(shù): 14/23頁(yè)
文件大?。?/td> 169K
代理商: PCA9500
Philips Semiconductors
Product data sheet
PCA9500
8-bit I
2
C and SMBus I/O port with 2-kbit EEPROM
2004 Sep 30
14
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER
SPECIFICATION
Memory cell data retention
10 years minimum
Number of memory cell write cycles
100,000 cycles minimum
I
2
C-BUS TIMING CHARACTERISTICS
SYMBOL
I
2
C-bus timing
(see Figure 20; Note 2)
PARAMETER
MIN.
TYP.
MAX.
UNIT
f
SCL
t
SW
t
BUF
t
SU;STA
t
HD;STA
t
r
t
f
t
SU;DAT
t
HD;DAT
t
VD;DAT
t
SU;STO
NOTE:
2. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V
IL
and V
IH
with an input
voltage swing of V
SS
to V
DD
.
SCL clock frequency
400
kHz
tolerable spike width on bus
50
ns
μ
s
μ
s
μ
s
μ
s
μ
s
ns
bus free time
1.3
START condition set-up time
0.6
START condition hold time
0.6
SCL and SDA rise time
0.3
SCL and SDA fall time
0.3
data set-up time
250
data hold time
0
ns
μ
s
μ
s
SCL LOW to data out valid
1.0
STOP condition set-up time
0.6
PORT TIMING CHARACTERISTICS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
t
pv
t
ps
t
ph
Output data valid; C
L
100 pF
Input data setup time; C
L
100 pF
Input data hold time; C
L
100 pF
4
μ
s
0
μ
s
4
μ
s
handbook, full pagewidth
SCL
SDA
MBD820
BIT 0
LSB
(R/W)
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tSU;STO
tf
r
t
tBUF
tSU;STA
1 / fSCL
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
SW00561
PROTOCOL
Figure 20.
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