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參數(shù)資料
| 型號(hào)： | PC89C660 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類(lèi)： | 8位微控制器 |
| 英文描述： | 80C51 8-bit Flash microcontroller family |
| 中文描述： | 80C51的8位閃存微控制器系列 |
| 文件頁(yè)數(shù)： | 62/89頁(yè) |
| 文件大?。?/td> | 491K |
| 代理商： | PC89C660 |
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Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
62
ERAM
256, 768,
1792 OR 7936
BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
000
FF
00
FF
00
80
80
EXTERNAL
DATA
MEMORY
FFFF
0000
SU01712
FF/2FF/6FF/1FFF
Figure 54. Internal and External Data Memory Address Space with EXTRAM = 0
Hardware WatchDog Timer (One-Time Enabled
with Reset-Out for P89C660/662/664/668)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, user must write 01EH
and 0E1H in sequence to the WDTRST (SFR location 0A6H). When
WDT is enabled, it will increment every machine cycle while the
oscillator is running and there is no way to disable the WDT except
through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output reset HIGH pulse at the RST
pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to
the WDTRST (SFR location 0A6H). When WDT is enabled, the user
needs to service it by writing 01EH and 0E1H to WDTRST to avoid
WDT overflow. The 14-bit counter overflows when it reaches 16383
(3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This
means the user must reset the WDT at least every 16383 machine
cycles. To reset the WDT, the user must write 01EH and 0E1H to
WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When the WDT overflows, it will generate
an output RESET pulse at the RST pin. The RESET pulse duration
is 98
×
T
OSC
(6 clock mode; 196 in 12 clock mode), where
T
OSC
= 1/f
OSC
. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed
within the time required to prevent a WDT reset.
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