參數(shù)資料
型號(hào)： PC89C660
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 8位微控制器
英文描述： 80C51 8-bit Flash microcontroller family
中文描述： 80C51的8位閃存微控制器系列
文件頁(yè)數(shù)： 30/89頁(yè)
文件大?。?/td> 491K
代理商： PC89C660
Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
30
S
08H
SLA
W
A
DATA
A
S
BOTH MASTERS CONTINUE
WITH SLA TRANSMISSION
18H
28H
OTHER MASTER SENDS REPEATED
START CONDITION EARLIER
SU00975
Figure 12. Simultaneous Repeated START Conditions from 2 Masters
STA FLAG
TIME OUT
SDA LINE
SCL LINE
START CONDITION
SU00976
Figure 13. Forced Access to a Busy I
2
C Bus
I
2
C Bus Obstructed by a Low Level on SCL or SDA
An I
2
C bus hang-up occurs if SDA or SCL is pulled LOW by an
uncontrolled source. If the SCL line is obstructed (pulled LOW) by a
device on the bus, no further serial transfer is possible, and the
SIO1 hardware cannot resolve this type of problem. When this
occurs, the problem must be resolved by the device that is pulling
the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a
slave device out of bit synchronization), the problem can be solved
by transmitting additional clock pulses on the SCL line (see
Figure 14). The SIO1 hardware transmits additional clock pulses
when the STA flag is set, but no START condition can be generated
because the SDA line is pulled LOW while the I
2
C bus is considered
free. The SIO1 hardware attempts to generate a START condition
after every two additional clock pulses on the SCL line. When the
SDA line is eventually released, a normal START condition is
transmitted, state 08H is entered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is
transmitted while SDA is obstructed (pulled LOW), the SIO1
hardware performs the same action as described above. In each
case, state 08H is entered after a successful START condition is
transmitted and normal serial transfer continues. Note that the CPU
is not involved in solving these bus hang-up problems.
Bus Error
A bus error occurs when a START or STOP condition is present at
an illegal position in the format frame. Examples of illegal positions
are during the serial transfer of an address byte, a data, or an
acknowledge bit.
The SIO1 hardware only reacts to a bus error when it is involved in
a serial transfer either as a master or an addressed slave. When a
bus error is detected, SIO1 immediately switches to the “not
addressed” Slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 00H. This status
code may be used to vector to a service routine which either
attempts the aborted serial transfer again or simply recovers from
the error condition as shown in Table 8.
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