參數(shù)資料
型號: PC87393F-VJG
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 外設及接口
英文描述: 100-Pin LPC SuperI/O Devices for Portable Applications
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: TQFP-100
文件頁數(shù): 92/148頁
文件大?。?/td> 1733K
代理商: PC87393F-VJG
2.0 Device Architecture and Configuration (Continued)
48
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2.11.3
FDC Configuration Register
This register is reset by hardware to 24h.
Location:
Index F0h
Type:
R/W
Bit
76543210
Name
Four-Drive
Encode
Enable
TDR
Register
Mode
DENSEL
Polarity
Control
FDC 2Mbps
Enable
Write
Protect
PC-AT or
PS/2 Drive
Mode Select
Reserved
TRI-STATE
Control
Reset
00100100
Bit
Description
7
Four-Drive Encode Enable
0: Two oppy drives are directly controlled by DR1-0, MTR1-0.
1: Four oppy drives are controlled with the aid of an external decoder.
6
TDR Register Mode
0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are 111111b (default)
1: Enhanced drive mode
5
DENSEL Polarity Control
0: Active low for 500 Kbps, or 1 or 2 Mbps data rates
1: Active high for 500 Kbps, or 1 or 2 Mbps data rates (default)
4
FDC 2Mbps Enable. This bit is set only when a 2Mbps drive is used.
0: 2Mbps disabled and the FDC clock is 24 MHz (default)
1: 2Mbps enabled and the FDC clock is 48 MHz
3
Write Protect. This bit allows forcing of write protect functionality by software. When set, writes to the floppy
disk drive are disabled. This effect is identical to WP when it is active.
0: Write protected according to WP signal (default)
1: Write protected regardless of value of WP signal
2
PC-AT or PS/2 Drive Mode Select
0: PS/2 drive mode
1: PC-AT drive mode (default)
1
Reserved
0
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
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