參數(shù)資料
型號: PC87393F-VJG
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 外設及接口
英文描述: 100-Pin LPC SuperI/O Devices for Portable Applications
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: TQFP-100
文件頁數(shù): 81/148頁
文件大?。?/td> 1733K
代理商: PC87393F-VJG
2.0 Device Architecture and Configuration (Continued)
38
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2.10.1
SuperI/O ID Register (SID)
This register contains the identity number of the chip. Members of the PC8739x family are identified by the value EAh.
Location:
Index 20h
Type:
RO
2.10.2
SuperI/O Configuration 1 Register (SIOCF1)
Location:
Index 21h
Type:
Varies per bit
Bit
76543210
Name
Chip ID
Reset
EAh
Bit
76543210
Name
Pin
Function
Select Lock
Reserved
Number of DMA Wait
States
Number of I/O Wait
States
Software
Reset
Global
Device
Enable
Reset
00010001
Bit
Description
7
Pin Function Select Lock. This bit determines if the bits that select pin functions (located in the SIOCF1, 2, 3,
4, 5, 8 and A registers) are read only or read/write. When set to 1, this bit can only be cleared by a hardware
reset.
0: Bits are R/W
1: Bits are RO.
6
Reserved
5-4
Number of DMA Wait States. These are R/W bits.
Bits
Number
5 4
0 0
Reserved
0 1
Two (default)
1 0
Six
1 1
Twelve
3-2
Number of I/O Wait States. These are R/W bits.
Bits
Number
32
0 0
Zero (default)
0 1
Two
1 0
Six
1 1
Twelve
1
Software Reset. Read always returns 0. This is a R/W bit.
0: Ignored (default)
1: Resets all the logical devices that are affected by hardware reset (with the exception of Lock bits)
0
Global Device Enable. This bit controls the function enable of all the PC8739x logical devices, except X-Bus .
With the exception of X-Bus, it allows all logical devices to be disabled simultaneously by writing to a single bit.
This is a R/W bit.
0: All logical devices in the PC8739x are disabled (except X-Bus)
1: Each logical device is enabled according to its Activate register (Index 30h) (default)
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