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參數(shù)資料
| 型號(hào)： | PC87393F-VJG |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 100-Pin LPC SuperI/O Devices for Portable Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 101/148頁(yè) |
| 文件大?。?/td> | 1733K |
| 代理商： | PC87393F-VJG |
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2.0 Device Architecture and Configuration (Continued)
56
www.national.com
2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION
This section applies to the PC87392, PC87393 and PC87393F only.
2.15.1
General Description
The GPIO functional block includes 32 pins, arranged in four 8-bit ports (ports 0, 1, 2 and 3). All pins in ports 0 and 1 are
I/O, and have full event detection capability, enabling them to trigger the assertion of IRQ and SMI signals. Pins in ports 2
and 3 are I/O, but none of them has event detection capability. The twelve runtime registers associated with the four ports
are arranged in the GPIO address space as shown in Table 23. The GPIO base address is 16-byte aligned. Address bits 3-
0 are used to indicate the register offset.
Table 23. Runtime Registers in GPIO Address Space
2.15.2
Implementation
The standard GPIO port with event detection capability (such as ports 0 and 1) has four runtime registers. Each pin is asso-
ciated with a GPIO Pin Configuration register that includes seven configuration bits. Ports 2 and 3 are non-standard ports
that do not support event detection, and therefore differ from the generic model as follows:
q
They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers
GPEVEN2/3 and GPEVST2/3 are not available.
q
Only bits 3-0 are implemented in the GPIO Pin Conguration registers of ports 2 and 3. Bits 6-4, associated with the
event detection functionality, are reserved.
Offset
Mnemonic
Register Name
Port
Type
00h
GPDO0
GPIO Data Out 0
0
R/W
01h
GPDI0
GPIO Data In 0
RO
02h
GPEVEN0 GPIO Event Enable 0
R/W
03h
GPEVST0 GPIO Event Status 0
R/W1C
04h
GPDO1
GPIO Data Out 1
1
R/W
05h
GPDI1
GPIO Data In 1
RO
06h
GPEVEN1 GPIO Event Enable 1
R/W
07h
GPEVST1 GPIO Event Status 1
R/W1C
08h
GPDO2
Data Out 2
2
R/W
09h
GPDI2
Data In 2
RO
0Ah
GPDO3
Data Out 3
3
R/W
0Bh
GPDI3
Data In 3
RO
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PC87393VJG | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:IC, SUPER I/O DEVICE, TQFP-100, Logic Device Type:Buffer, Supply Voltage Min:3V, |
| PC87393-VJG | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:100-Pin LPC SuperI/O Devices for Portable Applications |
| PC87410 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PC87410 PCI-IDE Interface Controller |
| PC87410VLK | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| PC87413 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LPC ServerI/O for Servers and Workstations |
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