參數(shù)資料
型號: PC107AVZFU100LC
廠商: ATMEL CORP
元件分類: 外設(shè)及接口
英文描述: PCI Bridge Memory Controller
中文描述: MULTIFUNCTION PERIPHERAL, PBGA503
封裝: 33 X 33 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BGA-503
文件頁數(shù): 36/50頁
文件大?。?/td> 453K
代理商: PC107AVZFU100LC
36
PC107A [Preliminary]
2137C–HIREL–03/04
IEEE 1149.1 (JTAG) AC Timing
Specifications
Table 18 provides the JTAG AC timing specifications for the PC107A while in the JTAG
operating mode.
At recommended operating conditions (see Table 3 on page 12) with
LV
DD
= 3.3
±
0.3V
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test (other than TDI and TMS) signal input timing with respect to TCK.
3. Non-test (other than TDO) signal output timing with respect to TCK.
4. Timings are independent of the system clock (PCI_SYNC_IN).
Figure 24.
JTAG Clock Input Timing Diagram
Figure 25.
JTAG TRST Timing Diagram
Table 18.
JTAG AC Timing Specifications (Independent of PCI_SYNC_IN)
Num
Characteristics
(4)
Min
Max
Unit
Notes
TCK Frequency of Operation
0
25
MHz
1
TCK Cycle Time
40
ns
2
TCK Clock Pulse Width Measured at 1.5V
20
ns
3
TCK Rise and Fall Times
0
3
ns
4
TRST_ Setup Time to TCK Falling Edge
10
ns
(1)
5
TRST_ Assert Time
10
ns
6
Boundary Scan Input Data Setup Time
5
ns
(2)
7
Boundary Scan Input Data Hold Time
15
ns
(2)
8
TCK to Output Data Valid
0
30
ns
(3)
9
TCK to Output High Impedance
0
30
ns
(3)
10
TMS, TDI Data Setup Time
5
ns
11
TMS, TDI Data Hold Time
15
ns
12
TCK to TDO Data Valid
0
15
ns
13
TCK to TDO High Impedance
0
15
ns
TCK
2
2
1
VM
VM
VM
3
3
VM = Midpoint Voltage
4
5
TRST
TCK
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