參數(shù)資料
型號(hào)： PC107AVZFU100LC
廠商： ATMEL CORP
元件分類： 外設(shè)及接口
英文描述： PCI Bridge Memory Controller
中文描述： MULTIFUNCTION PERIPHERAL, PBGA503
封裝： 33 X 33 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BGA-503
文件頁(yè)數(shù)： 13/50頁(yè)
文件大?。?/td> 453K
代理商： PC107AVZFU100LC
13
PC107A [Preliminary]
2137C–HIREL–03/04
Figure 3 shows the supply voltage sequencing and separation cautions.
Figure 3.
Supply Voltage Sequencing and Separation Cautions
Notes:
1. Numbers associated with waveform separations correspond to caution numbers listed in Table 3, “Recommended Operating
Conditions,” on page 12.
2. Refer to “Power Supply Voltage Sequencing” on page 42 for additional information.
3. Refer to Table 10 on page 25 for additional information on PLL Relock and reset signal assertion timing requirements.
4. Refer to Table 11 on page 26 for additional information on reset configuration pin setup timing requirements.
5. HRESET must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the device to be in the
non-reset state.
6. HRESET_CPU negates 2
17
memory clock cycles after HRESET negates.
OVDD/BVDD/GVDD(LVDD at 3.3V ----)
VDD/AVDD/LAVDD
LVDD at 5V
Time
3.3V
5V
2.5V
0
6
9
8
8
9
5.7
D
Voltage
Regulator
Delay(2)
Reset
Configuration Pins
HRESET
asserted 255
external memory
Clock cycles
(3)
9 external memory
clock cycles setup time
(4)
HRESET_CPU
HRESET
Vdd Stable
See Note 1 below.
VM = 1.4V
VM = 1.4V
Maximum rise time must be less than
one external memory clock cycle
(5)
100
μ
s
PLL
Relock
Time
(3)
Power Supply Ramp Up
(2)
6
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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PC108 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | PNP | 25V V(BR)CEO | 100MA I(C) | TO-92
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