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參數(shù)資料
| 型號： | PC107AVZFU100LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PCI Bridge Memory Controller |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PBGA503 |
| 封裝： | 33 X 33 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BGA-503 |
| 文件頁數(shù)： | 26/50頁 |
| 文件大?。?/td> | 453K |
| 代理商： | PC107AVZFU100LC |
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26
PC107A [Preliminary]
2137C–HIREL–03/04
Input AC Timing
Specifications
Table 11 provides the input AC timing specifications. See Figure 13 on page 27 and Fig-
ure 14 on page 27.
At recommended operating conditions (see Table 3 on page 12) with GV
DD
= 3.3V
±
5%
and LV
DD
= 3.3
±
0.3V
Notes:
1. All memory, processor and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the
signal in question to the V
M
= 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is
the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges
occur on every rising and falling edge of PCI_SYNC_IN). See Figure 13.
2. All PCI signals are measured from OV
DD
/2 of the rising edge of PCI_SYNC_IN to 0.4*OV
DD
of the signal in question for 3.3 V
PCI signaling levels. See Figure 14.
3. Input timings are measured at the pin.
4. t
CLK
is the time of one SDRAM_SYNC_IN clock cycle.
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the
V
M
= 1.4V of the rising edge of the HRESET signal. See Figure 15 on page 27.
Table 11.
Input AC Timing Specifications
Num
Characteristics
Min
Max
Unit
Notes
10a
PCI Input Signals
Valid to PCI_SYNC_IN (Input Setup)
3.0
–
ns
(2)(3)
10b
Memory Interface Signals
Valid to SDRAM_SYNC_IN (Input Setup)
2.0
–
ns
(1)(3)
10c
Epic, Misc. Debug Input Signals
Valid to SDRAM_SYNC_IN (Input Setup)
2.0
–
ns
(1)(3)
10d
Two-wire interface Input Signals
Valid to SDRAM_SYNC_IN (Input Setup)
2.0
–
ns
(1)(3)
10e
Mode select Inputs
Valid to HRESET (Input Setup)
9*t
CLK
–
ns
(1)(3)(5)
10f
60x Processor Interface Signals
Valid to SDRAM_SYNC_IN (Input Setup)
2.0
–
ns
(1)(3)
11a1
PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold)
1.0
–
ns
(2)(3)
11a2
Memory Interface Signals
SDRAM_SYNC_IN to Inputs Invalid (Input Hold)
0.5
–
ns
(1)(3)
11a3
60x Processor Interface Signals
SDRAM_SYNC_IN to Inputs Invalid (Input Hold)
0
–
ns
(1)(3)
11b
HRESET to Mode select Inputs Invalid (Input Hold)
0
–
ns
(1)(3)(5)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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