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參數(shù)資料
| 型號： | PC107A |
| 廠商： | Atmel Corp. |
| 英文描述： | PCI Bridge Memory Controller |
| 中文描述： | PCI橋內存控制器 |
| 文件頁數(shù)： | 44/50頁 |
| 文件大?。?/td> | 453K |
| 代理商： | PC107A |
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44
PC107A [Preliminary]
2137C–HIREL–03/04
Pull-up/Pull-down
Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in
progress; therefore, they do not require pull-up resistors on the bus. The processor data
bus signals are: DH[0
–
31], DL[0
–
31], and PAR[0
–
7]. The memory data bus signals are:
MDH[0
–
31], MDL[0
–
31], and PAR/AR[0
–
7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity
bits (DL[0
–
31], DP[4
–
7], MDL[0
–
31], and PAR[4
–
7]) will be disabled, and their outputs
will drive logic zeros when they would otherwise normally be driven. For this mode,
these pins do not require pull-up resistors, and should be left unconnected by the sys-
tem to minimize possible output switching.
It is recommended that ARTRY, TA, and TS have weak pull-up resistors (2 k
–
10 k
)
connected to BV
DD
.
It is recommended that MTP[1
–
2] and TEST2 have weak pull-up resistor (2 k
–
10 k
)
connected to GV
DD
.
It is recommended that the following signals be pulled up to OV
DD
with weak pull-up
resistors (2 k
–
10 k
): SDA, SCL, TEST1, and FTP[3
–
3].
It is recommended that the following PCI control signals be pulled up to LV
DD
with weak
pull-up resistors (2 k
–
10 k
): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP,
TRDY and INTA. The resistor values may need to be adjusted stronger to reduce
induced noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[06
–
4], TCK,
TDI, TMS, and TRST, BR1, HRESET_CPU, MCP, QACK, SRESET, TEST and
TRIG_OUT. See Table 1, “PC107A Pinout Listing,” on page 5 for more information.
The following pins have internal pull-up resistors enabled only while device is in the
reset state: MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, SDBAO, and SDMA[10
–
1]. See
Table 1, “PC107A Pinout Listing,” on page 5 for more information.
The following pins are reset configuration pins: MDL0, FOE, RCS0, SDBAO, SDMA[10
–
1], and PLL_CFG[0
–
3]. These pins are sampled during reset to configure the device.
Any other unused active low input pins should be tied to a logic one level via weak pull-
up resistors (2 k
–
10 k
) to the appropriate power supply listed in Table 3 on page 12.
Unused active high input pins should be tied to GND via weak pull-down resistors
(2 k
–
10 k
).
相關PDF資料 |
PDF描述 |
|---|---|
| PC107AMGHU100L | PCI Bridge Memory Controller |
| PC107AMGHU100LC | PCI Bridge Memory Controller |
| PC107AMGHU100LD | PCI Bridge Memory Controller |
| PC107AMZFU100L | PCI Bridge Memory Controller |
| PC107AMZFU100LC | PCI Bridge Memory Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PC107AMGH100LC | 制造商:e2v technologies 功能描述:POWERPC 107 PCI BRIDGE / MEMORY CTRL'R REV.C - 100MHZ, 2.5V, HITCE, IND TEMP |
| PC107AMGHU100L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AMGHU100LC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AMGHU100LD | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
| PC107AMZFU100L | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:PCI Bridge Memory Controller |
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