參數(shù)資料
型號(hào)： PC107A
廠(chǎng)商： Atmel Corp.
英文描述： PCI Bridge Memory Controller
中文描述： PCI橋內(nèi)存控制器
文件頁(yè)數(shù)： 35/50頁(yè)
文件大?。?/td> 453K
代理商： PC107A
35
PC107A [Preliminary]
2137C–HIREL–03/04
EPIC Serial Interrupt Mode AC
Timing Specifications
Table 17 provides the EPIC serial interrupt mode AC timing specifications for the
PC107A.
At recommended operating conditions (see Table 3 on page 12) with
LV
DD
= 3.3
±
0.3V
Notes:
1. See the PC107A User’s Manual for a description of the EPIC Interrupt Control Register (EICR) describing S_CLK frequency
programming.
2. S_RST, S_FRAME, and S_INT shown in Figure 22 and Figure 23 depict timing relationships to sys_logic_clk and S_CLK
and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the PC107A User’s Manual for a
complete description of the functional relationships between these signals.
3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;
sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is
implemented and the DLL is locked. See the PC107A User’s Manual for a complete clocking description.
Figure 22.
EPIC Serial Interrupt Mode Output Timing Diagram
Figure 23.
EPIC Serial Interrupt Mode Input Timing Diagram
Table 17.
EPIC Serial Interrupt Mode AC Timing Specifications
Num
Characteristics
Min
Max
Unit
Notes
1
S_CLK Frequency
1/14 SDRAM_SYNC_IN
1/2 SDRAM_SYNC_IN
MHz
(1)
2
S_CLK Duty Cycle
40
60
%
3
S_CLK Output Valid Time
–
6
nS
4
Output Hold Time
0
–
nS
5
S_FRAME, S_RST Output Valid Time
–
1 sys_logic_clk period + 6
nS
(2)
6
S_INT Input Setup Time to S_CLK
1 sys_logic_clk period + 2
–
nS
(2)
7
S_INT Inputs Invalid (Hold Time) to S_CLK
–
0
nS
(2)
S_CLK
S_RST
VM
VM
VM
S_FRAME
sys_logic_clk3
VM
VM
VM
VM
4
3
5
4
S_CLK
S_INT
VM
6
7
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