參數(shù)資料
型號(hào)： PC107A
廠商： Atmel Corp.
英文描述： PCI Bridge Memory Controller
中文描述： PCI橋內(nèi)存控制器
文件頁(yè)數(shù)： 41/50頁(yè)
文件大?。?/td> 453K
代理商： PC107A
41
PC107A [Preliminary]
2137C–HIREL–03/04
Clock Relationships
Choice
The PC107A’s internal PLL is configured by the PLL_CFG[0
–
3] signals. For a given
PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set the Core/Mem-
ory/Processor PLL (VCO) frequency of operation for the PCI-to-
Core/Memory/Processor frequency multiplying, if any. All valid PLL configurations for
the PC107A are shown in Table 19.
Table 19.
PC107A Microprocessor PLL Configuration
Notes:
1. PLL_CFG[0–3] settings not listed (00000100, 0110, 0111, 1010, 1011, and 1110) are reserved.
2. In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal core directly, the PLL is disabled, and the PCI: core
mode is set for 1:1 mode operation. The AC timing specifications given in this document do not apply in PLL Bypass mode.
3. In Clock Off mode, no clocking occurs inside the PC107A regardless of the PCI_SYNC_IN input.
4. Limited due to maximum memory VCO = 200 MHz.
5. Limited due to minimum VCO = 100 MHz.
6. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
7. Limited by maximum memory bus speed.
Ref
PLL_CFG
[0
–
3]
(2)
66 MHz Part
100 MHz Part
PCI: Core
Ratio
VCO
Multiplier
PCI_SYNC_IN
Range (MHz)
Core/Mem/CPU
Range (MHz)
PCI_SYNC_IN
Range (MHz)
Core/Mem/CPU
Range (MHz)
1
0001
25
(5)
– 33
25 – 33
25
(5)
– 50
(4)
25 – 50
1
4
2
0010
13
(5)
– 16
(4)
26 – 34
13
(5)
– 25
(4)
26 – 50
2
4
3
0011
Bypass
Bypass
Bypass
Bypass
5
0101
25
(5)
– 33
50 – 66
25
(5)
– 50
50 – 100
2
2
8
1000
17
(5)
– 22
51 – 66
17
(5)
– 33
50 – 100
3
2
9
1001
34
(5)
– 44
51 – 66
33
(5)
– 66
50 – 100
1.5
2
A
1010
13
(4)
–
16
(7)
52–64
13
(4)
–
25
(7)
52–100
4
2
C
1100
20
(5)
– 26
50 – 65
20
(5)
– 40
50 – 100
2.5
2
D
1101
50
(5)
– 66
50 – 66
50
(5)
– 66
50 – 66
1
2
F
1111
Clock off
(3)
Not Usable
Clock off
(3)
Not Usable
Off
Off
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