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參數(shù)資料
| 型號： | PAC80 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | 在系統(tǒng)可編程模擬電路 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 342K |
| 代理商： | PAC80 |
Specifications ispPAC80
10
Theory of Operation (Continued)
PG2
bit-7
PG1
bit-6
A/B
bit-5
CAL
bit-4
X
bit-3
X
bit-2
X
bit-1
X
bit-0
Table 1. SPI Control Bit Sequence
Table 2. Gain Bit Settings
1X (0dB)
0
2X (6dB)
1
5X (14dB)
0
10X (20dB)
1
PG1
0
1
PG2
Gain Setting
Symbol
Name
Description
FreqRange Bit
Hi/Lo Frequency Range Bit
Depending on the corner frequency, the frequency range bit is automati-
cally set from within PAC-Designer to optimize the transfer function
response of the ispPAC80. Exists for both the A and B user strings. Can be
overridden from within PAC-Designer from the edit symbol dialog.
UES Bits
User Electronic Signature
These are uncommitted E2 bits that can be used to store device information
for future reference. The ispPAC80 contains 21 UES bits. These bits are
accessible from within PAC-Designer by using the Edit Symbol, UES Bits
command. Part of user configuration string A only.
Cap Bits
Capacitor Selection Bits
Varying length data words for each of the 7 configuration capacitors of the
ispPAC80. There is a complete set of 70 bits total for each user configura-
tion string, A and B.
A/B Bit
Initial Configuration Select
With the A/B bit set to “A” (a logic 0), the device will power up in the
configuration stored in user string A. The designations of A or B would have
been determined initially in the design environment using PAC-Designer.
It is also possible to designate the B user string as the initial or “wake up”
configuration, although this is not recommended as it blocks the algorithm
required to do a “blind” verification of the A configuration of a previously
programmed device. This is determined from within PAC-Designer in the
edit symbol dialog.
PG1 & PG2 Bits
Programmable Gain Bits
Contained only in the A configuration string. Can also be modified under
SPI control. Refer to Table 2 for bit setting specifics.
ESF
Electronic Security Fuse
Setting this bit causes all subsequent readouts of the device configuration
to be disabled (JTAG Verify commands). Can be reset by performing a
JTAG user (USRA) bulk erase commands and reprogramming the device.
This feature is used to prevent unauthorized readout of the device’s
configuration.
Table 3. JTAG User Configuration Bits
the “A” configuration memory hold the desired “wake up”
filter response.
A/B Configuration
Two complete configurations can be stored in the E2
memory of the ispPAC80. Selection of either the “A” or
“B” configuration in real time is accomplished with the
device in the SPI interface mode (ENSPI pin = logic high).
An eight-bit string is read into the ispPAC80 in the
following order: four “don’t care” bits followed by a CAL
command bit, the A/B configuration setting and gain bits
PG2 and PG1.
JTAG User Bits
There are a number of user configured E2 bits that control
various aspects of and can all be accessed somewhere
in either the pull-down menus or directly in the schematic
design entry screen of the PAC-Designer software inter-
face to the ispPAC80. See the online help associated
with the ispPAC80 in PAC-Designer for more details of
how to set/program various operation modes. The list of
control E2 bits available is listed in Table 3.
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