參數(shù)資料
型號: PAC80
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable Analog Circuit
中文描述: 在系統(tǒng)可編程模擬電路
文件頁數(shù): 15/19頁
文件大?。?/td> 342K
代理商: PAC80
Specifications ispPAC80
5
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Dynamic Performance
tckmin
Minimum Clock Period
200
ns
tckh
TCK High Time
50
ns
tckl
TCK Low Time
50
ns
tmss
TMS Setup Time
15
ns
tmsh
TMS Hold Time
10
ns
tdis
TDI Setup Time
15
ns
tdih
TDI Hold Time
10
ns
tdozx
TDO Float to Valid Delay
60
ns
tdov
TDO Valid Delay
60
ns
tdoxz
TDO Valid to Float Delay
60
ns
tpwp
Time for a programming operation
Executed in Run-Test/Idle
80
100
ms
tpwe
Time for an erase operation
Executed in Run-Test/Idle
80
100
ms
tpwcal1
Time for auto-cal operation on power-up
Automatically executed at power-up
250
ms
tcalmin
Minimum auto-cal pulse width
40
ns
tpwcal2
Time for user initiated auto-cal operation
Executed on rising edge of CAL
100
ms
Timing Specifications (JTAG Interface Mode)
TA = 25°C; VS = +5.0V (Unless otherwise specified)
tckmin
tckh
tckl
tmss
tdis
tmsh
tdih
tdozx
tdov
tdoxz
TCK
TMS
TDI
TDO
tmss
TCK
TMS
tpwp, tpwe
*(PRGUSR/UBE executed in
Run-Test/Idle state)
CAL
(Note: CAL internally
initiated at device turn-on.)
VOUT = 0VDIFF
V
OUT
tpwcal1, tpwcal2
tcalmin
*Note: During device JTAG programming, analog output response will deviate from expected behavior. This is because all
configuration information is erased and then re-written as part of a normal programming cycle, momentarily changing device filter
and gain parameters. Behavior will deviate from that expected during both of these steps since the analog outputs are not clamped
during a programming cycle. During erase, a drop in the filter corner frequency and an automatic change to the 10X gain setting
can be expected (80ms minimum by specification) and will continue until bits go to there final state after a JTAG write command
is issued (less than 2ms later, though the write cycle must still be maintained for a full 80ms to achieve specified data retention).
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