- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄369945 > P8XC591 (NXP Semiconductors N.V.) HiRel FPGA, Low-Power 1.0?? CMOS Technology PDF資料下載
參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 84/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)當(dāng)前第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)
2000 Jul 26
84
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.2.12.4 SI, the Serial Interrupt Flag
SI = “1”: When the SI flag is set, then, if the EA and ES1
(interrupt enable register) bits are also set, a serial
interrupt is requested. SI is set by hardware when one of
25ofthe26possibleSIO1statesisentered.Theonlystate
that does not cause SI to be set is state F8H, which
indicates that no relevant state information is available.
WhileSIisset,thelowperiodoftheserialclockontheSCL
line is stretched, and the serial transfer is suspended. A
high level on the SCL line is unaffected by the serial
interrupt flag. SI must be reset by software.
SI = 0: When the SI flag is reset, no serial interrupt is
requested, and there is no stretching of the serial clock on
the SCL line.
15.2.12.5 AA, the Assert Acknowledge flag
AA = “1”: If the AA flag is set, an acknowledge (low level to
SDA) will be returned during the acknowledge clock pulse
on the SCL line when:
The “own slave address” has been received
The general call address has been received while the
general call bit (GC) in S1ADR is set
A data byte has been received while SIO1 is in the
master receiver mode
A data byte has been received while SIO1 is in the
addressed slave receiver mode
AA = “0”: if the AA flag is reset, a not acknowledge (high
level to SDA) will be returned during the acknowledge
clock pulse on SCL when:
A data has been received while SIO1 is in the master
receiver mode
A data byte has been received while SIO1 is in the
addressed slave receiver mode
When SIO1 is in the addressed slave transmitter mode,
state C8H will be entered after the last serial is transmitted
(see Figure 40). When SI is cleared, SIO1 leaves state
C8H, enters the not addressed slave receiver mode, and
the SDA line remains at a high level. In state C8H, the AA
flag can be set again for future address recognition.
When SIO1 is in the not addressed slave mode, its own
slave address and the general call address are ignored.
Consequently, no acknowledge is returned, and a serial
interrupt is not requested. Thus, SIO1 can be temporarily
released from the I
2
C bus while the bus status is
monitored. While SIO1 is released from the bus, START
and STOP conditions are detected, and serial data is
shiftedin.Addressrecognitioncanberesumedat anytime
by setting the AA flag. If the AA flag is set when the parts
own slave address or the general call address has been
partly received, the address will be recognized at the end
of the byte transmission.
15.2.12.6 CR0, CR1, and CR2, the Clock Rate Bits
These three bits determine the serial clock frequency
when SIO1 is in a master mode. The various serial rates
are shown in Table 57.
A 12.5 kHz bit rate may be used by devices that interface
to the I
2
C bus via standard I/O port lines which are
software driven and slow. 100kHz is usually the maximum
bit rate and can be derived from a 16 MHz, 12 MHz, or a
6 MHz oscillator. A variable bit rate (0.5 kHz to 62.5 kHz)
may also be used if Timer 1 is not required for any other
purpose while SIO1 is in a master mode.
The frequencies shown in Table 57 are unimportant when
SIO1 is in a slave mode. In the slave modes, SIO1 will
automatically synchronize with any clock frequency up to
100 kHz.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P90CE201 | 16-bit microcontroller |
| P90CE201AEB | 16-bit microcontroller |
| P9217 | PbS photoconductive detector |
| P930 | CdS photoconductive cell |
| PA025XSB | This technical specification applies to 2.5inch color TFT-LCD panel. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P8XC592 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCE598 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCL580HFH | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8XCL580HFT | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8Z77 DELUXE | 制造商:Asus 功能描述:P8Z77-V Deluxe ATX Motherboard |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。