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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 120/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
120
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
17 WATCHDOG TIMER (T3)
In addition to Timer T2 and the standard timers, a
Watchdog Timer (T3) is also incorporated on the
P8xC591.ThepurposeofaWatchdogTimeristoresetthe
microcontroller if it enters erroneous processor states
(possibly caused by electrical noise or RFI) within a
reasonable period of time. An analogy is the “dead man’s
handle” in railway locomotives. When enabled, the
watchdog circuitry will generate a system reset if the user
program fails to reload the Watchdog Timer within a
specified length of time known as the “watchdog interval”.
Watchdog Circuit Description:
The watchdog timer (Timer T3) consists of an 8-bit timer
with an 11-bit prescaler as shown in Figure 46. The
prescaler is fed with a signal whose frequency is
1
6
the
oscillator frequency (1 MHz with a 6 MHz oscillator). The
8-bit timer is incremented every “t” seconds, where:
T3 is incremented every 1024
μ
s, derived from the
oscillator frequency of 12 MHz by the following formula:
t = 6 x 2048 x 1/f
CLK
= 1024
μ
s at f
CLK
= 12 MHz.
If the 8-bit timer overflows, a short internal reset pulse is
generated which will reset the P8xC591. A short output
reset pulse is also generated at the RST pin. This short
output pulse (3 machine cycles) may be destroyed if the
RST pin is connected to a capacitor. This would not,
however, affect the internal reset operation.
Watchdog operation is activated by setting the ‘WDE’ bit in
Special Function Register AUXR1. Once ‘WDE’ is set, it
can only be disabled by applying a reset.
How to Operate the Watchdog Timer:
The watchdog timer has to be reloaded within periods that
are shorter than the programmed watchdog interval;
otherwise the watchdog timer will overflow and a system
reset will be generated. The user program must therefore
continually execute sections of code which reload the
watchdog timer. The period of time elapsed between
executionofthesesectionsofcode mustneverexceed the
watchdog interval. When using a 12 MHz oscillator, the
watchdog interval is programmable between 1024
μ
s and
261 ms.
In order to prepare software for watchdog operation, a
programmer should first determine how long his system
can sustain an erroneous processor state. The result will
be the maximum watchdog interval. As the maximum
watchdog interval becomes shorter, it becomes more
difficult for the programmer to ensure that the user
program always reloads the watchdog timer within the
watchdog interval, and thus it becomes more difficult to
implement watchdog operation.
The programmer must now partition the software in such a
way that reloading of the watchdog is carried out in
accordance with the above requirements. The programmer
must determine in execution times of all software modules.
The effect of possible conditional branches, subroutines,
external and internal interrupts must all be taken into
account. Since it may be very difficult to evaluate the
execution times of some sections of code, the programmer
should use worst case estimations. In any event, the
programmer must make sure that the watchdog is not
activated during normal operation.
The watchdog timer is reloaded in two stages in order to
prevent erroneous software from reloading the watchdog.
First PCON.4 (WLE) must be set. The T3 may be loaded.
When T3 is loaded, PCON.4 (WLE) is automatically reset.
T3 cannot be loaded if PCON.4 (WLE) is reset. Reload code
may be put in a subroutine as it is called frequently. Since
Timer T3 is an up-counter, a reload value of 00H gives the
maximum watchdog interval and a reload value of 0FFH
gives the minimum watchdog interval.
In the Idle mode, the watchdog circuitry remains active.
When watchdog operation is implemented, the Power-down
mode cannot be used since both states are contradictory.
Thus, when watchdog operation is enabled by setting ‘WDE’
bit in AUXR1.4, it is not possible to enter the Power-down
mode, and an attempt to set the Power-down bit (PCON.1)
will have no effect. PCON.1 will remain at logic 0.
Watchdog Software Example:
The following example shows how watchdog operation
might be handled in a user program.
; at the program start:
T3
EQU
0FFH ;address of watchdog
timer T3
PCON
WATCH-INTV EQU
EQU
087H ;address of PCON SFR
156
;watchdog interval
(e.g., 2 x 100 ms)
;to be inserted at each watchdog location within
;the user program:
LCALL WATCHDOG
;watchdog service routine:
WATCHDOG:
ORL
PCON,#10H ;set condition flag
(PCON.4)
;load T3 with
watchdog interval
MOV T3,WATCH-INV
RET
If its possible for this subroutine to be called in an erroneous
state, then the condition flag WLE should be set at different
parts of the main program.
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