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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 26/160頁(yè) |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
26
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.2.1
I
NTERFACE
M
ANAGEMENT
L
OGIC
(IML)
The Interface Management Logic interprets commands
from the CPU, controls addressing of the CAN Registers
and provides interrupts and status information to the CPU.
Additionally it drives the universal interface of the PeliCAN.
12.2.2
T
RANSMIT
B
UFFER
(TXB)
The Transmit Buffer is an interface between the CPU and
the Bit Stream Processor (BSP) and is able to store a
complete CAN message which should be transmitted over
the CAN network. The buffer is 13 bytes long, written by
the CPU and read out by the BSP or the CPU itself.
12.2.3
R
ECEIVE
B
UFFER
(RXB, RXFIFO)
The Receive Buffer is an interface between the
Acceptance Filter and the CPU and stores the received
and accepted messages from the CAN Bus line. The
Receive Buffer (RXB) represents a CPU-accessible
13-byte-window of the Receive FIFO (RXFIFO), which has
a total length of 64 bytes. With the help of this FIFO the
CPU is able to process one message while other
messages are being received.
12.2.4
A
CCEPTANCE
F
ILTER
(ACF)
The Acceptance Filter compares the received identifier
with the Acceptance Filter Table contents and decides
whether this message should be accepted or not. In case
of a positive acceptance test, the complete message is
stored in the RXFIFO. The ACF contains 4 independent
Acceptance Filter banks supporting extended and
standard CAN frames with “change on the fly” feature.
12.2.5
B
IT
S
TREAM
P
ROCESSOR
(BSP)
The Bit Stream Processor is a sequencer, controlling the
datastreambetweentheTransmitBuffer,RXFIFOandthe
CAN-Bus. It also performs the error detection, arbitration,
stuffing and error handling on the CAN bus.
12.2.6
E
RROR
M
ANAGEMENT
L
OGIC
(EML)
The EML is responsible for the error confinement of the
transfer-layer modules. It gets error announcements from
the BSP and then informs the BSP and IML about error
statistics.
12.2.7
B
IT
T
IMING
L
OGIC
(BTL)
The Bit Timing Logic monitors the serial CAN bus line and
handles the Bus line-related bit timing. It synchronizes to
the bit stream on the CAN Bus on a “recessive” to
“dominant” Bus line transition at the beginning of a
message (hard synchronization) and resynchronizes on
further transitions during the reception of a message (soft
synchronization). The BTL also provides programmable
time segments to compensate for the propagation delay
times and phase shifts (e.g., due to oscillator drifts) and to
define the sampling time and the number of samples to be
taken within a bit time.
12.2.8
T
RANSMIT
M
ANAGEMENT
L
OGIC
(TML)
The Transmit Management Logic provides the driver
signals for the push-pull CAN TX transistor stage.
Depending on the programmable output driver
configuration the external transistors are switched on or
off. Additionally a short circuit protection and the
asynchronous float on hardware reset is performed here.
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