參數(shù)資料
型號： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 64/160頁
文件大小： 601K
代理商： P8XC591
2000 Jul 26
64
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
With the baud rate generator as clock source for the serial
port in Mode 1 and Mode 3, the baud rate of can be
determined as follows:
Mode 1, 3 baud rate =
Baud rate generator overflow rate =
2
12
- S0PS with S0PS = S0PSH.3 - 0, S0PSL.7 - 0.
S0PS: Baud Rate Generator Prescaler load value
Table 47 lists baud rates and how they can be obtained
from the Internal Baud Rate Generator.
14.3.8
U
SING
T
IMER
1
TO
G
ENERATE
B
AUD
R
ATES
In Mode 1 and 3 of the serial port also timer 1 can be used
for generating baud rates. Then the baud rate is
determined by the timer 1 overflow rate and the value of
SMOD1 as follows:
SMOD1
(baud rate generator overflow rate)
osciillator frequency
×
32
×
-----------2
TheTimer 1interruptisusuallydisabledinthisapplication.
Timer 1 itself can be configured for either “timer” or
“counter” operation, and in any of its operating modes. In
most typical applications, it is configured for “timer”
operation in the auto-reload (high nibble of TMOD =
0010B). In this case the baud rate is given by the formula:
Very low baud rates can be achieved with Timer 1 if
leavingtheTimer 1interruptenabled,configuringthetimer
to run as 16-bit timer (high nibble of TMOD = 0001B), and
using the Timer 1 interrupt for a 16-bit software reload.
Table 49 lists lower baud rates and how they can be
obtained from Timer 1.
Mode 1, 3 baud rate
SMOD1
32
2
(timer 1 overflow rate)
×
=
Mode1 3 baud rate =2
SMOD1
256
TH1
(
–
(
×
6
32
)
)
×
--------------------------oscillator frequency
Table 44
Serial Port Control Register SCON (address)
Table 45
Description of S0PSH and S0PSL bits
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
BIT
SYMBOL
DESCRIPTION
7
6
5
SM0
SM1
SM2
See Table 46.
See Table 46.
Enables the multiprocessor communication feature in Modes 2 and 3.
In Mode 2 or
3, if SM2 is set to 1, then RI will not be activated if the received 9
th
data bit (RB8) is 0. In
Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In
Mode 0, SM2 should be 0.
Enables serial reception.
Set by software to enable reception. Clear by software to
disable reception.
The 9
th
data bit that will be transmitted in Modes 2 and 3.
Set or clear by software as
desired.
In Modes 2 and 3, is the 9
th
data bit that was received.
In Mode 1, if SM2 = 0, RB8 is
the stop bit that was received. In Mode 0, RB8 is not used.
Transmit interrupt flag.
Set by hardware at the end of the 8
th
bit time in Mode 0, or at
the beginning of the stop bit in the other modes, in any serial transmission. Must be
cleared by software.
Receive interrupt flag.
Set by hardware at the end of the 8
th
bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial reception (except see
SM2). Must be cleared by software.
4
REN
3
TB8
2
RB8
1
TI
0
RI
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