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參數(shù)資料
| 型號： | P89V52X2FA,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 31/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 44-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 1,300 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1002-ND - USB IN-CIRCUIT PROG LPC9XX |
| 其它名稱： | 568-4249-5 935282528512 P89V52X2FA |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
37 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
An assembly language routine to load the page register and perform an erase/program
operation is shown below. This code assumes the data EEPROM has been mapped into
user code space.
;**************************************************
;*
pgm user code
*
;**************************************************
;*
*
;* Inputs:
*
;*R3 = number of bytes to program (byte)
*
;*R4 = page address MSB(byte)
*
;*R5 = page address LSB(byte)
*
;*R7 = pointer to data buffer in RAM(byte)
*
;* Outputs:
*
;*R7 = status (byte)
*
;* C = clear on no error, set on error
*
;**************************************************
Table 34.
Flash Memory Control register (FMCON - address E4H) bit description
Bit
Symbol
Access
Description
0
ERR
R
Set when either of the following conditions occur:
Device was reset before the operation was completed.
Attempt made to access data EEPROM while Data Access Protect (DAP) is set.
An error occurs in the device’s internal high voltage circuits.
FMCMD.0
W
Command byte bit 0.
1
SV
R
Security violation. Set when an attempt is made to program, erase, or CRC a secured page.
The specic cause of the security violation depends on the operation:
PROG or EP: CSEC.0 = 1 or DPxSEC.1 = 1 for the page addressed by FMADRH/L.
ERS_G: Any DPxSEC.0 = 1.
ERS_DP: DPxSEC.2 = 1 for addressed page while in execution mode.
CRC_DP: DPxCSEC.0 = 1 and DPxSEC.1 = 0.
FMCMD.1
W
Command byte bit 1
2
-
R
Reserved
FMCMD.2
W
Command byte bit 2.
3
-
R
Reserved
FMCMD.3
W
Command byte bit 3.
4
DAP
R
Data Access Protect. When set, access to the data EEPROM is unmapped and thus
prohibited. Set by the MAP command. Cleared by the UNMAP command.
FMCMD.4
W
Command byte bit 4.
5
-
R
Reserved
FMCMD.5
W
Command byte bit 5.
6
WE
R
When set, indicates that data EEPROM writes during program execution are enabled.
FMCMD.6
W
Command byte bit 6.
7
BUSY
R
Indicates that a program, erase, CRC calculation or similar operation is in progress. Note that
this bit is usable only in ICP mode since the CPU is stalled whenever this bit is set in execution
mode.
FMCMD.7
W
Command byte bit 7.
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