參數(shù)資料
型號: P89V52X2FA,512
廠商: NXP Semiconductors
文件頁數(shù): 28/57頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 44-PLCC
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 1,300
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 192 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1012-ND - BOARD FOR P89V52X2 44-TQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1002-ND - USB IN-CIRCUIT PROG LPC9XX
其它名稱: 568-4249-5
935282528512
P89V52X2FA
P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
34 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
The data EEPROM must be mapped into the code memory address space in order to
read, erase, or program the data EEPROM. The memory is read using the MOVC
instruction.
6.13.1 Features
ICP with industry-standard commercial programmers
IAP-Lite allows individual and multiple bytes of data EEPROM to be programmed
under control of the end application.
Programming and erase over the full operating voltage range
Programming/Erase using ICP or IAP-Lite
Program or erases requires 2 ms, 4 ms, or 6 ms, depending on the operation
Programmable security for the data in each page
> 100000 typical erase/program cycles for each byte
Data EEPROM mapped into code space for quick MOVC reading
6.13.2 Register interface
Erasing, programming, and mapping operations are performed in the application under
the control of the microcontroller’s rmware using four SFRs and an internal 64-byte ‘page
register’. These SFRs are:
FMCON (Flash Control Register). When read, this is the status register. When written,
this is a command register. Note that the status bits are cleared to logic 0s when the
command is written.
FMADRL, FMADRH (Flash memory address low, Flash memory address high). Used
to specify the byte address within the page register or specify the page within user
code memory (for programming, erase, and reading the data EEPROM is mapped
into the user address space (see Table 32).
FMDATA (Flash Data Register). Accepts data to be loaded into the page register.
Data is read by mapping the data EEPROM into the code memory space and using the
MOVC instruction.
6.13.3 Mapping the data EEPROM into code space
In order to read, erase, or program the data EEPROM must be mapped into the code
memory address space. This is accomplished by writing the MAP command (09H) to
FMCON. The data EEPROM may be unmapped by writing the UNMAP command (0AH)
to FMCON. The mapping of the data EEPROM pages into code memory space is shown
6.13.4 Reading the data EEPROM
Reading the data EEPROM can be achieved by performing the following sequence:
Table 32.
Data EEPROM page addresses
Data EEPROM page
Start address End address
0
FF00H
FF3FH
1
FF40H
FF7FH
2
FF80H
FFBFH
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