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參數(shù)資料
| 型號： | P89V52X2FA,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 30/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 44-PLCC |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 1,300 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1002-ND - USB IN-CIRCUIT PROG LPC9XX |
| 其它名稱： | 568-4249-5 935282528512 P89V52X2FA |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
36 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
Writing either the PROG or EP command to FMCON will start the program or
erase-program process and place the CPU in a program-idle state. The CPU will remain
in this idle state until the program or erase-program cycle is completed. Interrupts will NOT
be serviced until the cycle is completed.
Erase-program or programming of a single byte (or multiple bytes) in the data EEPROM
array is accomplished using the following steps:
Write the LOAD command (00H) to FMCON. The LOAD command will clear all
locations in the page register and their corresponding update ags.
Write the address within the page register to FMADRL. Since the loading the page
register uses FMADRL[5:0], and since the erase-program or program command uses
FMADRH and FMADRL[7:6], the user can write the byte location within the page
register (FMADRL[5:0]) and the code memory page address (FMADRH and
FMADRL[7:6]) at this time.
Write the data to be programmed to FMDATA. This will increment FMADRL pointing to
the next byte in the page register.
Write the address of the next byte to be programmed to FMADRL, if desired. (This is
not needed for contiguous bytes since FMADRL is auto-incremented). All bytes to be
programmed must be within the same page.
Write the data for the next byte to be programmed to FMDATA.
Repeat writing of FMADRL and/or FMDATA until all desired bytes have been loaded
into the page register.
Write the page address mapped into user code memory to FMADRH and
FMADRL[7:6], if not previously included when writing the page register address to
FMADRL[5:0].
Write the EP (68H) or PROG (48H) command to FMCON, starting the erase-program
or program cycle.
Read FMCON to check status. If aborted, repeat starting with the LOAD command.
Table 33.
Flash Memory Control register (FMCON - address F4H) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol (R)
BUSY
WE
-
DAP
-
SV
ERR
Symbol (W)
FMCMD.7
FMCMD.6
FMCMD.5
FMCMD.4
FMCMD.3
FMCMD.2
FMCMD.1
FMCMD.0
Reset
0000000
0
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