參數(shù)資料
型號: P89LPC9402FBD,557
廠商: NXP Semiconductors
文件頁數(shù): 20/60頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 64-LQFP
標(biāo)準(zhǔn)包裝: 450
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LCD,LED,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 935288631557
P89LPC9402_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 22 April 2009
27 of 60
NXP Semiconductors
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
7.18.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.18.3 Mode 2
Mode 2 congures the Timer register as an 8-bit Counter with automatic reload. Mode 2
operation is the same for Timer 0 and Timer 1.
7.18.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is
in Mode 3 it can still be used by the serial port as a baud rate generator.
7.18.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
7.18.6 Timer overow toggle output
Timers 0 and 1 can be congured to automatically toggle a port output whenever a timer
overow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the rst
timer overow when this mode is turned on.
7.19 RTC/system timer
The P89LPC9402 has a simple RTC that allows a user to continue running an accurate
timer while the rest of the device is powered down. The RTC can be a wake-up or an
interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a
16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded
again and the RTCF ag will be set. The clock source for this counter can be either the
CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog reset will
reset the RTC and its associated SFRs to the default state.
The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and
RTCDATH registers.
7.20 UART
The P89LPC9402 has an enhanced UART that is compatible with the conventional 80C51
UART except that Timer 2 overow cannot be used as a baud rate source. The
P89LPC9402 does include an independent Baud Rate Generator. The baud rate can be
selected from the oscillator (divided by a constant), Timer 1 overow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.20.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB rst. The baud rate is xed at 1
16 of the CPU clock
frequency.
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