參數(shù)資料
型號： P89LPC9402FBD,557
廠商： NXP Semiconductors
文件頁數(shù)： 14/60頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 8K 64-LQFP
標(biāo)準(zhǔn)包裝： 450
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 18MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LCD，LED，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤
其它名稱： 935288631557
P89LPC9402_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 22 April 2009
21 of 60
NXP Semiconductors
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC9402 has 8 kB of on-chip Code memory.
7.12 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 6.
7.13 Interrupts
The P89LPC9402 uses a four priority level interrupt structure. This allows great exibility
in controlling the handling of the many interrupt sources. The P89LPC9402 supports
13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port
RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard,
comparators 1 and 2, SPI.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
7.13.1 External interrupt inputs
The P89LPC9402 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request ag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC9402 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
Table 6.
On-chip data memory usages
Type
Data RAM
Size (bytes)
DATA
Memory that can be addressed directly and indirectly
128
IDATA
Memory that can be addressed indirectly
256
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P89LPC9408FBD557 制造商:NXP Semiconductors 功能描述:P89LPC9408FBD/LQFP64/TRAYDPM//
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