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參數(shù)資料
| 型號： | P87CL881H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM(帶63K字節(jié)OTP程序存儲器和2K字節(jié)RAM的低壓微控制器) |
| 中文描述： | 低63字節(jié)OTP程序存儲器和2K字節(jié)RAM電壓微控制器（帶檢察官辦公室63K字節(jié)程序存儲器和2K字節(jié)的RAM的低壓微控制器） |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 139K |
| 代理商： | P87CL881H |
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1999 Apr 16
13
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
6.3
Internal data memory
The internal data memory is divided into three physically
separated parts:
256 bytes of RAM, 128 bytes of Special Function
Registers and 1792 bytes of AUX-RAM. These can be
addressed each in a different way (see also Table 4).
1.
RAM 0 to 127 can be addressed directly and indirectly
as in the 80C51; address pointers are R0 and R1 of
the selected register-bank
2.
RAM 128 to 255 can only be addressed indirectly;
address pointers are R0 and R1 of the selected
register bank
3.
AUX-RAM 0 to 1791 is indirectly addressable via the
AUX-RAM Page Register (XRAMP) and MOVX-Ri
instructions, unless it is disabled by setting ARD = 1.
AUX-RAM 0 to 1791 is also indirectly addressable as
external data memory via MOVX-datapointer
instruction, unless it is disable by setting ARD = 1.
When executing from internal program memory, an
access to AUX-RAM 0 to 1791 when ARD = 0 will not
affect the ports P0, P2, P3.6 and P3.7.
An access to external data memory locations higher
than 1791 will be performed with the MOVX @ DPTR
instructions in the same way as in the 80C51 structure, so
with P0 and P2 as data/address bus and P3.6 and P3.7 as
write and read timing signals. Note that the external data
memory cannot be accessed with R0 and R1 as address
pointer if the AUX-RAM is enabled (ARD = 0, default after
reset).
The Special Function Registers (SFR) can only be
addressed directly in the address range from 128 to 255.
Four register banks, each 8 registers wide, occupy
locations 0 through 31 in the lower RAM area. Only one of
these banks may be enabled at a time. The next 16 bytes,
locations 32 through 47, contain 128 directly addressable
bit locations. The stack can be located anywhere in the
internal 256 bytes RAM. The stack depth is only limited by
the available internal RAM space of 256 bytes (see Fig.4).
Table 4
Internal data memory map
LOCATION
ADDRESS
ADDRESSING
RAM
AUX-RAM
RAM
SFR
0 to 127
0 to 1791
128 to 255
128 to 255
direct and indirect
indirect only with MOVX
indirect only
direct only
Fig.4 Memory map.
handbook, full pagewidth
MGL618
INTERNAL
(EA = 1)
FBFFH
EXTERNAL
(EA = 0)
FFFFH
FFFFH
0
0
00H
0000H
7FH
FFH
INDIRECT
ADDRESSING
DIRECT
PAGE 0
PAGE 1
PAGE 2
PAGE 3
PAGE 4
PAGE 5
PAGE 6
EXTERNAL DATA
MEMORY
DATA MEMORY
INTERNAL
AUX-RAM
(ARD = 0)
PROGRAM MEMORY
INTERNAL RAM
INDIRECT AND
DIRECT
ADDRESSING
0700H
06FFH
(ARD = 1)
(ARD = 0/1)
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