- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄367739 > P87CL881H (NXP Semiconductors N.V.) Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM(帶63K字節(jié)OTP程序存儲(chǔ)器和2K字節(jié)RAM的低壓微控制器) PDF資料下載
參數(shù)資料
| 型號(hào)： | P87CL881H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM(帶63K字節(jié)OTP程序存儲(chǔ)器和2K字節(jié)RAM的低壓微控制器) |
| 中文描述： | 低63字節(jié)OTP程序存儲(chǔ)器和2K字節(jié)RAM電壓微控制器（帶檢察官辦公室63K字節(jié)程序存儲(chǔ)器和2K字節(jié)的RAM的低壓微控制器） |
| 文件頁(yè)數(shù)： | 10/32頁(yè) |
| 文件大?。?/td> | 139K |
| 代理商： | P87CL881H |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)
1999 Apr 16
10
Philips Semiconductors
Product specification
Low-voltage microcontroller with 63-kbyte
OTP program memory and 2-kbyte RAM
P87CL881H
Notes
1.
2.
E7H and FDH are reserved locations and must not be written to.
Where: X = undefined state.
OTP interface
OTP Address High Register
OTP Address Low Register
OTP Data Register
OTP In-System Programming Register
OTP Test Register
OAH
OAL
ODATA
OISYS
OTEST
D5
D4
D6
DC
D7
X
00
X XXXX
XXXX XXXX
XXXX XXXX
000X 0000
0000 0000
REGISTER NAME
REGISTER MNEMONIC
SFR ADDRESS
RESET VALUE
(2)
6.2
I/O facilities
6.2.1
P
ORTS
The P87CL881 has 32 I/O lines treated as 32 individually
addressable bits or as four parallel 8-bit addressable ports.
Ports 0, 1, 2 and 3 perform the following alternative
functions:
Port 0 Provides the multiplexed low-order address and
data bus for expanding the device with standard
memories and peripherals.
Port 1 Used for a number of special functions:
P1.0 to P1.7 provides the inputs for the external
interrupts INT2 to INT9
P1.0/T2 and P1.1/T2EX for external inputs of Timer 2
P1.2/T2COMP for external activation and compare
output of Timer 2
P1.4/CLK for the clock output
P1.6/SCL and P1.7/SDA for the I
2
C-bus interface are
real open-drain outputs or high-impedance; no other
port configurations are available.
Port 2 Provides the high-order address bus when
expanding the device with external program
memory and/or external data memory.
Port 3 Pins can be configured individually to provide:
P3.0/RXD/data and P3.1/TXD/clock which are serial
port receiver input and transmitter output (UART)
P3.2/INT0 and P3.3/INT1 are external interrupt request
inputs
P3.4/T0 and P3.5/T1 as counter inputs
P3.6/WR and P3.7/RD are control signals to write and
read to external memories.
To enable a port pin alternative function, the port bit latch
in its SFR must contain a logic 1.
Each port consists of a latch (Special Function Registers
P0 to P3), an output driver and input buffer. All ports have
internal pull-ups. Figure 3(a) shows that the strong
transistor P1 is turned on for only 1 oscillator period after a
LOW-to-HIGH transition in the port latch. When on, it turns
on P3 (a weak pull-up) through the inverter IN1. This
inverter and transistor P3 form a latch which holds the
logic 1.
6.2.2
P
ORT
I/O
CONFIGURATION
I/O port output configurations are determined by the
settings in the port configuration SFRs. Each port has two
associated SFRs: PnCFGA and PnCFGB, where ‘n’
indicates the specific port number (0 to 3). One bit in each
of the 2 SFRs relates to the output setting for the
corresponding port pin, allowing any combination of the
2 output types to be mixed on those port pins.
For example, the output type of P1.3 is controlled by
setting bit 3 in the SFRs P1CFGA and P1CFGB.
The port pins may be individually configured via the SFRs
with one of the following modes (P1.6 and P1.7 can be
open-drain or high-impedance but never have any diodes
against V
DD
).
Mode 0 Open-drain; quasi-bidirectional I/O with
n-channel open-drain output. Use as an output
(e.g. Port 0 for external memory accesses
(EA = 0) or access above the built-in memory
boundary) requires the connection of an external
pull-up resistor. The ESD protection diodes
against V
DD
and V
SS
are still present. Except for
the I
2
C-bus pins P1.6 and P1.7, ports which are
configured as open-drain still have a protection
diode to V
DD
. See Fig.3a.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P87LPC762BD512 | IC-SM-8-BIT MCU |
| P87LPC762FD512 | IC-SM-8-BIT MCU |
| P87LPC764 | Low power. low price. low pin count (20 pin) microcontroller with 4 kbyte OTP |
| P87LPC764 | Low power, low price, low pin count(20 pin) microcontroller with4 kB OTP(帶4 kB OTP的低功耗，低價(jià)格，少引腳（20引腳）的微控制器) |
| P87LPC767 | Low power, low price, low pin count 20 pin microcontroller with 4-kbyte OTP and 8-bit A/D converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P87L42 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER |
| P87LPC759 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP |
| P87LPC759BN | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP |
| P87LPC760 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Low power, low price, low pin count (14 pin) microcontroller with 1 kbyte OTP |
| P87LPC760BDH | 功能描述:8位微控制器 -MCU 80C51 1K/128 OTP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。