參數(shù)資料
型號(hào)： P82C150AFT
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： CAN Serial Linked I/O device SLIO with digital and analog port functions
中文描述： 1 CHANNEL(S), 125K bps, LOCAL AREA NETWORK CONTROLLER, PDSO28
封裝： 7.50 MM, PLASTIC, SO-28
文件頁(yè)數(shù)： 25/36頁(yè)
文件大?。?/td> 209K
代理商： P82C150AFT
1996 Jun 19
25
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with
digital and analog port functions
P82C150
11 APPLICATION INFORMATION
11.1
Maximum bus length
The bit timing parameters refer to using a P8xCE598 or
P8xC592 microcontroller with on-chip CAN interface as a
host node (see Fig.20).
11.1.1
A
SSUMPTIONS
The total in/out delay of external transceiver circuit is
less than 180 ns (e.g. PCA82C250 CAN transceiver;
see Fig.20).
The propagation delay on the transmission medium is
5.0 ns/m.
Table 15
Maximum bus length for CAN-bus systems with P82C150 nodes.
Notes
1.
t
prop
is the maximum propagation delay between two CAN-bus nodes (delays of on- and off-chip transceiver circuits
included).
BTR0 and BTR1 (hex values) are particular configuration registers referring to bit timing.
2.
BIT RATE
(kbit/s)
t
prop
(1)
(
μ
s)
INDICATION
FOR MAXIMUM
BUS LENGTH
(m)
BIT TIMING (P8xCE598/P8xC592)
f
CLK
(MHz)
BTR0
(2)
BTR1
(2)
125
0.8
25
15
C5H
34H
100
1
45
16
C7H
34H
50
2
145
16
CFH
34H
20
5
445
16
E7H
34H
11.2
Start up sequence
The following start-up sequence, illustrated by
Figures 10 and 11, shows a simple example how
P82C150 nodes can be controlled from a host node. This
application example works with different system
configurations:
One conventional crystal-controlled CAN node and one
or more P82C150 nodes.
More than one conventional crystal-controlled CAN
node and one or more P82C150 nodes.
Fig.10 General start-up procedure for CAN-bus
systems with P82C150 nodes.
handbook, halfpage
Power-on
MHA077
Initialization of host node's CAN controller
Wait until all P82C150 nodes are assumed
to have finished Power-on-reset
Periodic calibration
(transmit calibration message with a
repetition period of maximum 8000 bit times)
Start-up bit time calibration procedure
(1)
(1) See Fig.11.
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