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參數(shù)資料
| 型號(hào)： | P82C150AFT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CAN Serial Linked I/O device SLIO with digital and analog port functions |
| 中文描述： | 1 CHANNEL(S), 125K bps, LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, SO-28 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 209K |
| 代理商： | P82C150AFT |
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1996 Jun 19
10
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with
digital and analog port functions
P82C150
7.2.1
D
ATA
I
NPUT
R
EGISTER
(A
DDRESS
0)
This read only register contains the states of port pins
P15 to P0 which are transmitted on request, or
automatically by change of one of the input levels,
provided that the respective input is configured to event
capture mode (see Table 3). When an edge is detected
the port state is loaded into the transmit buffer after the
Control Field of the triggered message is sent. Therefore a
delay for input settling is provided. If between edge
detection and transmission of the data input register
another input signal change at the input port occurs, the
corresponding data input register bit is overwritten by the
current input port value. Additionally the register content is
sent automatically after wake-up or bus mode change,
once the bit time has been calibrated (part of the ‘sign-on’
message).
7.2.2
P
OSITIVE
E
DGE
R
EGISTER
(A
DDRESS
1)
This write only register contains configuration information
per port pin for the event capture facility.
The corresponding PE-bit (see Table 3) has to be set to
logic 1 to enable capturing of the rising edge.
7.2.3
N
EGATIVE
E
DGE
R
EGISTER
(A
DDRESS
2)
This write only register contains configuration information
per port pin for the event capture facility.
The corresponding NE-bit (see Table 3) has to be set to
logic 1 to enable capturing of the falling edge.
The combination of PE and NE functions is possible.
7.2.4
D
ATA
O
UTPUT
R
EGISTER
(A
DDRESS
3)
This write only register contains the output data for the port
pins. The output drivers are bitwise enabled by OE
(see Section 7.2.5). New data for the output port register
are processed and written to the output ports directly after
the corresponding CAN message to the P82C150 is
successfully checked and becomes valid.
7.2.5
O
UTPUT
E
NABLE
R
EGISTER
(A
DDRESS
4)
This write only register controls the output drivers of the
port pins. The corresponding Output Enable Register bit
has to be set to logic 1 to enable an output driver. If set to
logic 0, the corresponding output driver is disabled
(floating; see Fig.7).
Table 3
X = don’ t care; n = 0 to 15.
Programming of the I/O registers to event capture on edge or to digital output
FUNCTION
REGISTER CONTENTS OF PARTICULAR PORT PIN
POSITIVE EDGE
(BITS PEn)
NEGATIVE EDGE
(BITS NEn)
OUTPUT ENABLE
(BITS OEn)
Digital output
X
X
1
Digital input
Polling
Event capture on edge
Rising
Falling
Rising and Falling
X
X
X
1
0
1
0
1
1
X
X
X
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相關(guān)代理商/技術(shù)參數(shù) |
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| P82C150AHT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CAN Serial Linked I/O device SLIO with digital and analog port functions |
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