參數(shù)資料
型號: P4C1256L-70CMB
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 32K X 8 STANDARD SRAM, 70 ns, CDIP28
封裝: 0.300 INCH, CERAMIC, SIDE BRAZED, DIP-28
文件頁數(shù): 5/16頁
文件大?。?/td> 1155K
代理商: P4C1256L-70CMB
W39L040
Publication Release Date: April 14, 2005
- 13 -
Revision A6
6.8 Embedded #Data Polling Algorithm
Start
Read Byte
(DQ0 - DQ7)
Address = VA
Pass
DQ7 = Data
?
Yes
No
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during sector
erase operation
= Any of the device addresses being erased
during chip erase operation
= Any of the page addresses within
the page being erased during page
erase operation
6.9 Embedded Toggle Bit Algorithm
Start
Read Byte
(DQ0 - DQ7)
Address = Don't Care
DQ6 = Toggle
?
Yes
No
Pass
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