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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
924
Freescale Semiconductor
23.0.5.8
Port D Data Direction Register (DDRD)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
23.0.5.9
Port E Data Register (PORTE)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
7
6
5
4
3
2
1
0
R
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
W
Reset
0
0
0
0
0
0
0
0
Figure 23-10. Port D Data Direction Register (DDRD)
Table 23-11. DDRD Field Descriptions
Field
Description
7–0
DDRD[7:0]
Data Direction Port D — This register controls the data direction for port D. DDRD determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note:
Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTD after changing the DDRD register.
7
6
5
4
3
2
1
0
R
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
W
Alt.
Func.
XCLKS
or
ECLKX2
MODB
or
TAGHI
MODA
or
RE
or
TAGLO
ECLK
EROMCTL
or
LSTRB
or
LDS
R/W
or
WE
IRQ
XIRQ
Reset
0
0
0
0
0
0
—
1
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
—
1
= Unimplemented or Reserved
Figure 23-11. Port E Data Register (PORTE)