
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.17
450
Freescale Semiconductor
Read: For transmit buffers, anytime when TXEx flag is set (see
Section 10.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)
”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)
”). For receive buffers,
only when RXF flag is set (see
Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)
”).
Write: For transmit buffers, anytime when TXEx flag is set (see
Section 10.3.2.7, “MSCAN Transmitter
Flag Register (CANTFLG)
”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)
”). Unimplemented for
receive buffers.
Reset: Undefined (0x00XX) because of RAM-based implementation
10.3.3.1
Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE,
and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0],
RTR, and IDE bits.
10.3.3.1.1
IDR0–IDR3 for Extended Identifier Mapping
Figure 10-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
IDR0
R
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
W
IDR1
R
ID2
ID1
ID0
RTR
IDE (=0)
W
IDR2
R
W
IDR3
R
W
= Unused, always read ‘x’
7
6
5
4
3
2
1
0
R
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
W
Reset:
x
x
x
x
x
x
x
x
Figure 10-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping