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Chapter 12 Serial Peripheral Interface (S12SPIV4)
MC9S12XDP512 Data Sheet, Rev. 2.17
532
Freescale Semiconductor
Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and
is transferred to the parallel SPI data register after the last bit is shifted in.
After the 16th (last) SCK edge:
DatathatwaspreviouslyinthemasterSPIdataregistershouldnowbeintheslavedataregisterand
the data that was in the slave data register should be in the master.
The SPIF flag in the SPI status register is set, indicating that the transfer is complete.
Figure 12-11
is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for
CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because
theSCK,MISO,andMOSIpinsareconnecteddirectlybetweenthemasterandtheslave.TheMISOsignal
is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master
must be either high or reconfigured as a general-purpose output not affecting the SPI.
Figure 12-11. SPI Clock Format 0 (CPHA = 0)
t
L
Begin
End
SCK (CPOL = 0)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
SEL SS (O)
Master only
Transfer
SCK (CPOL = 1)
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
t
L
= Minimum leading time before the first SCK edge
t
T
= Minimum trailing time after the last SCK edge
t
I
= Minimum idling time between transfers (minimum SS high time)
t
L
, t
T
, and t
I
are guaranteed for the master mode and required for the slave mode.
MSB
LSB
LSB
MSB
Bit 5
Bit 2
Bit 6
Bit 1
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
CHANGE O
MISO pin
SEL SS (I)
t
T
I
for t
T
, t
l
, t
L
Minimum 1/2 SCK
t
I
t
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK Edge Number
End of Idle State
Begin of Idle State