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參數(shù)資料
| 型號(hào)： | P0120004P |
| 廠商： | SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC. |
| 英文描述： | 1.5W GaAs Power FET (Pb-Free Type) |
| 中文描述： | 1.5W GaAs功率場效應(yīng)管（無鉛型） |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 599K |
| 代理商： | P0120004P |
Caution: Power Supply Sequence
For safe operation, electric power should be supplied in
following sequence. First, the negative voltage should be
applied on the gate, and the voltage should be more negative
than the pinch-off voltage when you turn on the power
supply. Then, drain bias can be applied. Finally, you can turn
on the RF signal.
When turning off the power supply, the sequence should be
(1)RF signal (2)Drain (3)Gate.
Vo
Dr
Vo
Bias Circuit
Specifications and information are subject to change without notice. 2003-11
Sumitomo Electric Industries, Ltd. 1,Taya-cho, Sakae-ku, Yokohama, 244-8588 Japan
Phone: +81-45-853-7263 Fax: +81-45-853-1291 e-mail :
GaAsIC-ml@ml.sei.co.jp
Web Site:
www.sei.co.jp/GaAsIC/
-9-
Technical Note
P0120004P
1.5W GaAs Power FET (Pb-Free Type)
SUMITOMO ELECTRIC
If you used Ids other than 400mA, you can calculate the
resistance values as follows:
R4 set to be 1k
I
1
: Ic of Q1a
I
2
:Ic of Q1b
V
be1
: Vbe of Q1a V
be2
: Vbe of Q1b
R1=(+6V-Vds+V
be2
-V
be1
)/I
1
=(+6V-Vds)/I
1
R2=(Vds-V
be2
)/I
1
R3=(+6V-Vds)/(Ids+I
2
)
R5=|-5V-Vgs|/I
2
Attention to Heat Radiation
In the layout design of the printed circuit board (PCB) on
which the power FETs are attached, the heat radiation to
minimize the device junction temperature should be taken
into account, since it significantly affects the MTTF and RF
performance. In any environment, the junction temperature
should be lower than the absolute maximum rating during
the device operation and it is recommended that the thermal
design has enough margin.
P0110004P
P0120004P
Application
Circuit
R4
Q1a
GND
R2
Vgs
+6V
Vds
R1
-5V
R3
R5
Q1b
GND
Gate
ltage
0V
Bias Voltage
ain
ltage
On
On
0V
More Than 1mS
Off
Bias Voltage
More Than 1mS
Off
Vds
Ids
Q1
R1
R2
R3
R4
R5
+5.9V
400mA
UMT1N (Rohm)
20
1/10W
1.8k
1/10W
0.15
RL series (SUSUMU)
1k
1/10W
1.3k
1/10W
[Passive Biasing]
If you use a fixed bias circuit, you sometimes need to control
the gate bias to get the same Ids, since the devices have some
margin of pinch-off voltage (Vp) variation depending on the
wafer lots. If you employ a fixed Vgs biasing for your
system, you should closely monitor the drain current,
particularly when new wafer lots are introduced.
[Active Biasing]
We recommend using an active bias circuit, which can
eliminate the influence of Vp variation. An example of an
active bias circuit called “current mirror ” is shown below.
Here, two PNP transistors having the minimum variation of
Ibe characteristics are used. These transistors adjust Vgs by
changing Vds automatically. It will realize the constant
current characteristics, regardless of the temperature.
The circuit should be connected directly in line with where
the voltage supplies would be normally connected with the
application circuit. Of course a matching circuit is required,
but it is not shown in this figure.
[Note]
In the measurements of RF performance (Pout vs Pin, etc)
using the application circuit described before, the active bias
circuit herein was not utilized. The application circuits were
biased directly from two power supplies.
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