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參數(shù)資料
| 型號： | OX16CF950 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW COST ASYNCHRONOUS 16 BIT CARD |
| 中文描述： | 低成本異步16位卡 |
| 文件頁數(shù)： | 36/60頁 |
| 文件大小： | 753K |
| 代理商： | OX16CF950 |
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unused data format. Writing 0xBF to LCR will set LCR[7]
but leaves LCR[6:0] unchanged. Therefore, the data format
of the transmitter and receiver data is not affected. Write
the desired LCR value to exit from this selection.
Note: In-band transmit and receive flow control is disabled
in 9-bit mode.
EFR[1:0]: In-band receive flow control mode
When in-band receive flow control is enabled, the UART
compares the received data with te programmed XOFF
character(s). When this occurs, the UART will disable
transmission as soon as any current character
transmission is complete. The UART then compares the
received data with the programmed XON character(s).
When a match occurs, the UART will re-enable
transmission (see section 6.11.6).
For automatic in-band flow control, bit 4 of EFR must be
set. The combinations of software receive flow control can
be selected by programming EFR[1:0] as follows:
logic [00]
In-band receive flow control is disabled.
logic [01]
Single character in-band receive flow control
enabled, recognising XON2 as the XON
character and XOFF2 as the XOFF
character.
logic [10]
Single character in-band receive flow control
enabled, recognising XON1 as the XON
character and XOFF1 and the XOFF
character.
logic [11]
The behaviour of the receive flow control is
dependent on the configuration of EFR[3:2].
single character in-band receive flow control
is enabled, accepting both XON1 and XON2
as valid XON characters and both XOFF1
and XOFF2 as valid XOFF characters when
EFR[3:2] = “01” or “10”. EFR[1:0] should not
be set to “11” when EFR[3:2] is either “00”.
EFR[3:2]: In-band transmit flow control mode
When in-band transmit flow control is enabled, XON/XOFF
character(s) are inserted into the data stream whenever the
RFL passes the upper trigger level and falls below the
lower trigger level respectively.
For automatic in-band flow control, bit 4 of EFR must be
set. The combinations of software tansmit flow control can
then be selected by programming EFR[3:2] as follows:
logic [00]
In-band transmit flow control is disabled.
logic [01]
Single character in-band transmit flow
control enabled, using XON2 as the XON
character and XOFF2 as the XOFF
character.
Page 36
OXCF950 DATA SHEET V1.1
OXFORD SEMICONDUCTOR LTD.
logic [10]
Single character in-band transmit flow
control enabled, using XON1 as the XON
character and XOFF1 as the XOFF
character.
Logic[11]
The value EFR[3:2] = “11” is reserved for
future use and should not be used
EFR[4]: Enhanced mode
logic 0
Non-Enhanced mode. Disables IER bits 47,
ISR bits 4-5, FCR bits 4-5, MCR bits 5-7 and
in-band flow control. Whenever this bit is
cleared, the setting of other bits of EFR are
ignored.
logic 1
Enhanced mode. Enables the Enhanced Mode
functions. These functions include enabling
IER bits 4-7, FCR bits 4-5, MCR bits 5-7. For
in-band flow control the software driver must
set this bit first. If this bit is set, out-of-band
flow control is configured with EFR bits 6-7,
otherwise
out-of-band
compatible with 16C750.
EFR[5]: Enable special character detection
logic 0
Special character detection is disabled.
logic 1
While in Enhanced mode (EFR[4]=1), the
UART compares the incoming receiver data
with the XOFF2 value. Upon a correct match,
the received data will be transferred to the
RHR and a level 5 interrupt (XOFF or special
character) will be asserted if level 5 interrupts
are enabled (IER[5] set to 1).
EFR[6]: Enable automatic RTS flow control.
logic 0
RTS flow control is disabled (default).
logic 1
RTS flow control is enabled in Enhanced mode
(i.e. EFR[4] = 1), where the RTS# pin will be
forced inactive high if the RFL reaches the
upper flow control threshold. This will be
released when the RFL drops below the lower
threshold. The 650 and 950 software drivers
should use this bit to enable RTS flow control.
The 750 compatible driver uses MCR[5] to
enable RTS flow control.
EFR[7]: Enable automatic CTS flow control.
logic 0
CTS flow control is disabled (default).
logic 1
CTS flow control is enabled in Enhanced mode
(i.e. EFR[4] = 1), where the data transmission
is prevented whenever the CTS# pin is held
inactive high. The 650 and 950 software
drivers should use this bit to enable CTS flow
control. The 750 compatible driver uses
MCR[5] to enable CTS flow control.
flow
control
is
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