參數(shù)資料
型號(hào)： OX16CF950
廠商： Electronic Theatre Controls, Inc.
英文描述： LOW COST ASYNCHRONOUS 16 BIT CARD
中文描述： 低成本異步16位卡
文件頁數(shù)： 24/60頁
文件大?。?/td> 753K
代理商： OX16CF950
enabled using the Additional Control Register ‘ACR’ (see
section 6.11.3). In addition to larger FIFOs and higher baud
rates, the enhancements of the 950 over the 16C654 are:
Selectable arbitrary trigger levels for the receiver and
transmitter FIFO interrupts
Improved automatic flow control using selectable
arbitrary thresholds
DSR#/DTR# automatic flow control
Transmitter and receiver can be optionally disabled
Software reset of device
Readable FIFO fill levels
Optional generation of an RS-485 buffer enable signal
Four-byte device identification (0x16C95006)
Readable status for automatic in-band and outof-
band flow control
External 1x clock modes (see section 6.10.4)
Flexible “M N/8” clock prescaler (see section 6.10.2)
Programmable sample clock to allow data rates up to
15 Mbps (see section 6.10.3) at 5V
9-bit data mode
The 950 trigger levels are enabled when ACR[5] is set (bits
4 to 7 of FCR are ignored). Then arbitrary trigger levels can
be defined in RTL, TTL, FCL and FCH registers (see
section 6.11). The Additional Status Register (‘ASR’) offers
flow control status for the local and remote transmitters.
FIFO levels are readable using RFL and TFL registers.
The UART has a flexible prescaler capable of dividing the
system clock by any value between 1 and 31.875 in steps
of 0.125. It divides the system clock by an arbitrary value in
Page 24
OXCF950 DATA SHEET V1.1
OXFORD SEMICONDUCTOR LTD.
“M N/8” format, where M and N are 5 and 3bit binary
numbers programmed in CPR[7:3] and CPR[2:0]
respectively. This arrangement offers a great deal of
flexibility when choosing an input clock frequency to
synthesize arbitrary baud rates. The default division value
is 4 to provide backward compatibility with 16C650
devices.
The user may apply an external 1x (or Nx) clock for the
transmitter and receiver to the RI# and DSR# pin
respectively. The transmitter clock may be asserted on the
DTR# pin. The external clock options are selected through
the CKS register (offset 0x02 of ICR).
It is also possible to define the over-sampling rate used by
the transmitter and receiver clocks. The 16C450/16C550
and compatible devices employ 16 times over-sampling,
i.e. There are 16 clock cycles per bit. However, the 950 can
employ any over-sampling rate from 4 to 16 by
programming the TCR register. This allows the data rates
to be increased to 460.8 Kbps using a 1.8432MHz clock, or
15 Mbps using a 60 MHz clock (at 5V). The default value
after a reset for this register is 0x00, which corresponds to
a 16 cycle sampling clock. Writing 0x01, 0x02 or 0x03 will
also result in a 16 cycle sampling clock. To program the
value to any value from 4 to 15 it is necessary to write this
value into TCR i.e. to set the device to a 13 cycle sampling
clock it would be necessary to write 0x0D to TCR. For
further information see sections 6.10.3.
The 950 also offers 9bit data frames for multi-drop
industrial applications.
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