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參數(shù)資料
| 型號： | OX16C954-PCC60-B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 5/54頁 |
| 文件大小： | 529K |
| 代理商： | OX16C954-PCC60-B |
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Data Sheet Revision 1.0
Page 5
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
1
P
ERFORMANCE
C
OMPARISON
Feature
OX16C954
16C454
16C554
16C654
16C750
Integrated Serial channels
Good-Data status
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS#flow
Auto DSR#/DTR#flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmtter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
4
4
No
No
4
No
No
4
No
No
1
No
No
Yes
Yes
15 Mbps
60 Mbps
128
Yes
Yes
Yes
Yes
128
128
128
Yes
Yes
Yes
248
Yes
Yes
Yes
Yes
Yes
Yes
115 kbps
n/a
1
No
No
No
No
1
1
n/a
No
n/a
n/a
n/a
No
No
No
No
No
No
115 kbps
n/a
16
No
No
No
No
4
1
n/a
No
No
No
n/a
No
No
No
No
No
No
1.5 Mbps
n/a
64
Yes
Yes
Yes
No
4
4
4
No
No
No
2
No
No
No
No
No
Yes
1 Mbps
n/a
64
Yes
No
Yes
No
4
1
n/a
No
No
No
n/a
No
No
No
No
No
No
Table 1 OX16C954 performance compared with 16C454, 16C554, 16C654 and 16C750 devices
Improvements of the OX16C954 over previous generations of PC UARTs:
Deeper FIFOs:
The OX16C954 offers 128-byte deep FIFOs for the
transmtter and receiver.
Higher data rates:
Transmssion and reception baud rates up to 15Mbps. A
flexible clock prescaler offers division ratios of 1 to 31 7/8
in steps of 1/8 using a divide-by-“MN/8” circuitry. The
flexible prescaler allows users to select froma wide variety
of input clock frequencies as well as access to higher baud
rates whilst maintaining compatibility with existing software
drivers (see section 14.2).
External clock option:
The receiver can accept an external clock on the DSR#
input. The transmtter can accept a 1x clock on the RI#
input and/or assert its own (Nx) clock on the DTR#output.
In 1x mode, asynchronous data may be transmtted and
received at speeds up to 60 Mbps (see section 14.6).
Automatic flow control:
The UART automatically handles either or both in-band
(software) flow control (transmtting and receiving Xon/Xoff
characters) and out-of-band (hardware) flow control using
the RTS#/CTS#or DSR#/DTR#modemcontrol lines.
Special character detection:
The receiver can be programmed to generate an interrupt
upon reception of a particular character value.
Power-down:
The device can be placed in ‘sleep mode’ to conserve
power
Readable FIFO levels:
Driver efficiency can be improved by using readable FIFO
levels.
Selectable trigger levels:
The receiver FIFO threshold can be arbitrarily
programmed. The transmtter FIFO threshold and
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