參數(shù)資料
型號(hào)： OX16C954-PCC60-B
廠商： Electronic Theatre Controls, Inc.
英文描述： High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface
中文描述： UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口
文件頁(yè)數(shù)： 29/54頁(yè)
文件大小： 529K
代理商： OX16C954-PCC60-B
Data Sheet Revision 1.0
Page 29
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
In this mode, the receiver and transmtter interrupts are
fully operational. The modemcontrol interrupts are also
operational, but the interrupt sources are now the lower
four bits of the ModemControl Register instead of the four
modemstatus inputs. The interrupts are still controlled by
the IER.
MCR[5]: Enable XON-Any in Enhanced mode or enable
out-of-band flow control in non-Enhanced mode
650/950 (enhanced) modes:
logic 0
XON-Any is disabled.
logic 1
XON-Any is enabled.
In enhanced mode (EFR[4]=1), this bit enables the Xon-
Any operation. When Xon-Any is enabled, any received
data will be accepted as a valid XON (see in-band flow
control, section 13.3).
750 (normal) mode:
logic 0
CTS/RTS flow control disabled.
logic 1
CTS/RTS flow control enabled.
In non-enhanced mode, this bit enables the CTS/RTS out-
of-band flow control.
MCR[6]: IrDA mode
logic 0
Standard serial receiver and transmtter data
format.
logic 1
Data will be transmtted and received in IrDA
format.
This function is only available in Enhanced mode. It
requires a 16x clock to function correctly.
MCR[7]: Baud rate prescaler select
logic 0
Normal (divide by 1) baud rate generator
prescaler selected.
logic 1
Divide-by-“M+N/8”
prescaler selected.
where M& N are programmed in CPR (ICR offset 0x01).
After a hardware reset, CPR defaults to 0x20 (divide-by-4)
and MCR[7] is reset. User writes to this flag will only take
effect in Enhanced mode. See section 13.1.
baud
rate
generator
11.2 Modem Status Register ‘MSR’
MSR[0]: Delta CTS#
Indicates that the CTS#input has changed since the last
time the MSR was read.
MSR[1]: Delta DSR#
Indicates that the DSR#input has changed since the last
time the MSR was read.
MSR[2]: Trailing edge RI#
Indicates that the RI#input has changed fromlow to high
since the last time the MSR was read.
MSR[3]: Delta DCD#
Indicates that the DCD#input has changed since the last
time the MSR was read.
MSR[4]: CTS
This bit is the complement of the CTS#input. It is
equivalent to RTS (MCR[1]) in internal loop-back mode.
MSR[5]: DSR
This bit is the complement of the DSR#input. It is
equivalent to DTR (MCR[0]) in internal loop-back mode.
MSR[6]: RI
This bit is the complement of the RI#input. In internal loop-
back mode it is equivalent to the internal OUT1.
MSR[7]: DCD
This bit is the complement of the DCD#input. In internal
loop-back mode it is equivalent to the internal OUT2.
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