參數(shù)資料
型號(hào)： OV6120
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA
中文描述： 單芯片CMOS到岸價(jià)格彩色數(shù)碼攝像機(jī)
文件頁(yè)數(shù)： 30/31頁(yè)
文件大?。?/td> 341K
代理商： OV6120
OV6620/OV6120
30
Version 1.11
14 May 1999
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
O
MNI
V
ISION
T
ECHNOLOGIES
, Inc.
Advanc ed Information
Preliminary
2B
FRARL
5E
RW
Frame Rate Adjust Low
FRARL[7:0] - Lowest 8 bit of frame rate adjust control byte. Frame rate adjustment resolution
is 0.21%. Control byte is 10 bit. Every LSB equal decrease frame rate 0.21%. Range is
0.21% - 109%. IF frame rate adjustment enable, COME7 must set to “0”.
reserved
Common Control J
COMJ[7:5] - reserved
COMJ[4] - Enable auto black expanding mode.
COMJ[3] - “1” = White Balance update when AGC/AEC stable. “0” = White Balance register
update independent with AEC/AGC.
COMJ[2] - Band filter enable. After adjust frame rate to match indoor light frequency, this bit
enable a different exposure algorithm to cut light band induced by fluorescent light.
COMJ[1] - reserved
COMJ[0] - A/D U and V BLC separate mode. “1” = U and V offset cancelled by different
register. “0” = U V offset cancelled by one common register [2E].
V Channel Offset Adjustment
VCOFF[7]: Offset adjustment direction: “0” = Add V[6:0]; “1” = Substrate V[6:0].
VCOFF[6:0] - V channel digital output offset adjustment. Range: +128mV ~ -128mV. If
COMG[2]=0, this register will be updated by internal auto A/D BLC circuit, and write a value
to this register with I
2
C has no effect. If COMG[2] =1, V channel offset adjustment will use
the register stored value which can be changed by I
2
C. If COMF[1] =1, this register has no
effect to A/D output data. If output RGB raw data, this register will adjust R/G/B data.
Reserved
Color Processing Parameter Control
CPP[7:6] - reserved
CPP[5] - Luminance gamma on/off. “1” - luminance gamma on; “0” - luminance gamma is 1.
CPP[4:0] - reserved
Bias Adjustment
BIAS[7:6] - A/D reference level adjustment. [00] - 110% internal full signal range; [01] - 120%,
[10] - 130%, [11] - 140%.
BIAS[5:0] - reserved
reserved
reserved
reserved
Common Control K
COMK[7] - HREF edge latched by PCLK falling edge (When COMD[6] = 0). “0” HREF edge is
10 ns after PCLK rising edge.
COMK[6] - Output port drive current additional 2x control bit.
COMK[5] - reserved.
COMK[4] - ZV port Vertical timing selection. “1” VSYNC output ZV port vertical sync signal.
“0” = normal TV vertical sync signal.
COMK[3] - Quick stable mode when camera mode change. After relative control bit set, the
first VS will be the stable image with suitable AEC/AWB setting. “0” - slow mode, after mode
change need more field/frame to get stable AEC/AWB setting image.
COMK[2] - reserved
COMK[1] - AWB stable time selection when in slow mode. “1” - 4 times less time needed to get
stable AWB setting when in slow AWB mode.
COMK[0] -reserved.
Common Control L
COML[7] - reserved
COML[6] - PCLK output timing selection. 1 -- PCLK valid only when HREF is high; 0 -- PCLK is
free running.
COML[5] - Vertical sync selection, 1 -- Same period between 1st HREF and VS falling edge in
two field; 0 - Different timing period between 1st HREF and VS falling edge
COML[4] - “1” select CHSYNC output from HREF port. “0” normal
COML[3] - “1” select HREF output from CHSYNC port. “0” normal
COML[2] - Tristate all control signal output (FODD, CHSYNC, HREF, PCLK)
COML[1] - Highest 1 bit of horizontal sync starting position, combined with register [3A]
COML[0] - Highest 1 bit of horizontal sync ending position, combined with register [3B]
Horizontal Sync Start Position
HSST[7:0] - lower 8 bit of horizontal sync starting position, combined with register bit of
COML[1], total 9 bit control. range: [00] -- [FF]. HSEND[8:0] must less than HSST[8:0]
Horizontal Sync End Position
HEND[7:0] - lower 8 bit of horizontal sync ending position, combined with register bit of
COML[0], total 9 bit control. range: [00] -- [FF]. HSEND[8:0] must be larger than HSST[8:0]
2C
Rsvd2C
88
RW
2D
COMJ
03
RW
2E
VCOFF
80
RW
2F-32
Rsvd2F-Rsvd32
xx
-
33
CPP
00
RW
34
BIAS
A2
RW
35
36
37
Rsvd35
Rsvd36
Rsvd37
80
48
41
RW
RW
RW
38
COMK
81
RW
39
COML
00
RW
3A
HSST
0F
RW
3B
HSEND
3C
RW
Subad-
dress
(hex)
Register
Default
(hex)
Read/
Write
Descriptions
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