
OV6620/OV6120
24
 Version 1.11
14 May 1999
SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS
O
MNI
V
ISION
 T
ECHNOLOGIES
, Inc.
Advanc ed Information
Preliminary
3.1
In I
2
C operation, the master must perform the following
operations:
I
2
C Bus Protocol Format
n
n
n
Generate the start/stop condition
Provide the serial clock on 
SCL
Place the 7-bit slave address, the RW bit, 
and the 8-bit subaddress on 
SDA
The receiver must pull down SDA during the acknowl-
edge bit time. During the write cycle, the OV6620/
OV6120 device returns the acknowledgment and, dur-
ing read cycle, the master returns the acknowledgment
except when the read data is the last byte. If the read
data is the last byte, the master does not perform an
acknowledge, indicating to the slave that the read cycle
can be terminated. Note that the restart feature is not
supported here. 
Within each byte, MSB is always transferred first.
Read/write control bit is the LSB of the first byte.
Standard I
2
C communications require only two pins:
SCL and SDA. SDA is configured as open drain for bi-
directional purpose. A HIGH to LOW transition on the
SDA while SCL is HIGH indicates a START condition. A
LOW to HIGH transition on the SDA while SCL is HIGH
indicates a STOP condition. Only a master can gener-
ate START/STOP conditions. 
Except for these two special conditions, the protocol
that SDA remain stable during the HIGH period of the
clock, SCL. Each bit is allowed to change state only
when SCL is LOW (See Figure 9. Bit Transfer on the
I
2
C Bus and Figure 10. Data Transfer on the I
2
C Bus
below).
The OV6620/OV6120 I
2
C supports multi-byte write and
multi-byte read. The master must supply the subad-
dress. in the write cycle, but not in the read cycle. 
Figure 9. Bit Transfer on the I
2
C Bus
I
Figure 10. Data Transfer on the I
2
C Bus
SDA
SCL
DATA 
STABLE
DATA 
CHANGE
ALLOWED
SDA
SCL
S
P
A
A
A
SLAVE ID
RW
SUB ADD
DATA